/*
 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

/* This file is mechanically generated from RTL. Any hand-edits will be lost! */

#define QIB_7322_Revision_OFFS 0x0
#define QIB_7322_Revision_DEF 0x0000000002010601
#define QIB_7322_Revision_R_Simulator_LSB 0x3F
#define QIB_7322_Revision_R_Simulator_MSB 0x3F
#define QIB_7322_Revision_R_Simulator_RMASK 0x1
#define QIB_7322_Revision_R_Emulation_LSB 0x3E
#define QIB_7322_Revision_R_Emulation_MSB 0x3E
#define QIB_7322_Revision_R_Emulation_RMASK 0x1
#define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
#define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
#define QIB_7322_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
#define QIB_7322_Revision_BoardID_LSB 0x20
#define QIB_7322_Revision_BoardID_MSB 0x27
#define QIB_7322_Revision_BoardID_RMASK 0xFF
#define QIB_7322_Revision_R_SW_LSB 0x18
#define QIB_7322_Revision_R_SW_MSB 0x1F
#define QIB_7322_Revision_R_SW_RMASK 0xFF
#define QIB_7322_Revision_R_Arch_LSB 0x10
#define QIB_7322_Revision_R_Arch_MSB 0x17
#define QIB_7322_Revision_R_Arch_RMASK 0xFF
#define QIB_7322_Revision_R_ChipRevMajor_LSB 0x8
#define QIB_7322_Revision_R_ChipRevMajor_MSB 0xF
#define QIB_7322_Revision_R_ChipRevMajor_RMASK 0xFF
#define QIB_7322_Revision_R_ChipRevMinor_LSB 0x0
#define QIB_7322_Revision_R_ChipRevMinor_MSB 0x7
#define QIB_7322_Revision_R_ChipRevMinor_RMASK 0xFF

#define QIB_7322_Control_OFFS 0x8
#define QIB_7322_Control_DEF 0x0000000000000000
#define QIB_7322_Control_PCIECplQDiagEn_LSB 0x6
#define QIB_7322_Control_PCIECplQDiagEn_MSB 0x6
#define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1
#define QIB_7322_Control_PCIEPostQDiagEn_LSB 0x5
#define QIB_7322_Control_PCIEPostQDiagEn_MSB 0x5
#define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1
#define QIB_7322_Control_SDmaDescFetchPriorityEn_LSB 0x4
#define QIB_7322_Control_SDmaDescFetchPriorityEn_MSB 0x4
#define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1
#define QIB_7322_Control_PCIERetryBufDiagEn_LSB 0x3
#define QIB_7322_Control_PCIERetryBufDiagEn_MSB 0x3
#define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1
#define QIB_7322_Control_FreezeMode_LSB 0x1
#define QIB_7322_Control_FreezeMode_MSB 0x1
#define QIB_7322_Control_FreezeMode_RMASK 0x1
#define QIB_7322_Control_SyncReset_LSB 0x0
#define QIB_7322_Control_SyncReset_MSB 0x0
#define QIB_7322_Control_SyncReset_RMASK 0x1

#define QIB_7322_PageAlign_OFFS 0x10
#define QIB_7322_PageAlign_DEF 0x0000000000001000

#define QIB_7322_ContextCnt_OFFS 0x18
#define QIB_7322_ContextCnt_DEF 0x0000000000000012

#define QIB_7322_Scratch_OFFS 0x20
#define QIB_7322_Scratch_DEF 0x0000000000000000

#define QIB_7322_CntrRegBase_OFFS 0x28
#define QIB_7322_CntrRegBase_DEF 0x0000000000011000

#define QIB_7322_SendRegBase_OFFS 0x30
#define QIB_7322_SendRegBase_DEF 0x0000000000003000

#define QIB_7322_UserRegBase_OFFS 0x38
#define QIB_7322_UserRegBase_DEF 0x0000000000200000

#define QIB_7322_DebugPortSel_OFFS 0x40
#define QIB_7322_DebugPortSel_DEF 0x0000000000000000
#define QIB_7322_DebugPortSel_EnhMode_SrcMuxSelWrEn_LSB 0x3F
#define QIB_7322_DebugPortSel_EnhMode_SrcMuxSelWrEn_MSB 0x3F
#define QIB_7322_DebugPortSel_EnhMode_SrcMuxSelWrEn_RMASK 0x1
#define QIB_7322_DebugPortSel_EnhMode_SrcMuxSelIndex_LSB 0x35
#define QIB_7322_DebugPortSel_EnhMode_SrcMuxSelIndex_MSB 0x3E
#define QIB_7322_DebugPortSel_EnhMode_SrcMuxSelIndex_RMASK 0x3FF
#define QIB_7322_DebugPortSel_EnEnhancedDebugMode_LSB 0x34
#define QIB_7322_DebugPortSel_EnEnhancedDebugMode_MSB 0x34
#define QIB_7322_DebugPortSel_EnEnhancedDebugMode_RMASK 0x1
#define QIB_7322_DebugPortSel_EnDbgPort_LSB 0x33
#define QIB_7322_DebugPortSel_EnDbgPort_MSB 0x33
#define QIB_7322_DebugPortSel_EnDbgPort_RMASK 0x1
#define QIB_7322_DebugPortSel_DbgClkPortSel_LSB 0x2E
#define QIB_7322_DebugPortSel_DbgClkPortSel_MSB 0x32
#define QIB_7322_DebugPortSel_DbgClkPortSel_RMASK 0x1F
#define QIB_7322_DebugPortSel_SrcMuxSel1_LSB 0x26
#define QIB_7322_DebugPortSel_SrcMuxSel1_MSB 0x2D
#define QIB_7322_DebugPortSel_SrcMuxSel1_RMASK 0xFF
#define QIB_7322_DebugPortSel_SrcMuxSel0_LSB 0x1E
#define QIB_7322_DebugPortSel_SrcMuxSel0_MSB 0x25
#define QIB_7322_DebugPortSel_SrcMuxSel0_RMASK 0xFF
#define QIB_7322_DebugPortSel_DebugOutMuxSel_LSB 0x0
#define QIB_7322_DebugPortSel_DebugOutMuxSel_MSB 0x1
#define QIB_7322_DebugPortSel_DebugOutMuxSel_RMASK 0x3

#define QIB_7322_DebugPortNibbleSel_OFFS 0x48
#define QIB_7322_DebugPortNibbleSel_DEF 0xFEDCBA9876543210
#define QIB_7322_DebugPortNibbleSel_NibbleSel15_LSB 0x3C
#define QIB_7322_DebugPortNibbleSel_NibbleSel15_MSB 0x3F
#define QIB_7322_DebugPortNibbleSel_NibbleSel15_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel14_LSB 0x38
#define QIB_7322_DebugPortNibbleSel_NibbleSel14_MSB 0x3B
#define QIB_7322_DebugPortNibbleSel_NibbleSel14_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel13_LSB 0x34
#define QIB_7322_DebugPortNibbleSel_NibbleSel13_MSB 0x37
#define QIB_7322_DebugPortNibbleSel_NibbleSel13_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel12_LSB 0x30
#define QIB_7322_DebugPortNibbleSel_NibbleSel12_MSB 0x33
#define QIB_7322_DebugPortNibbleSel_NibbleSel12_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel11_LSB 0x2C
#define QIB_7322_DebugPortNibbleSel_NibbleSel11_MSB 0x2F
#define QIB_7322_DebugPortNibbleSel_NibbleSel11_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel10_LSB 0x28
#define QIB_7322_DebugPortNibbleSel_NibbleSel10_MSB 0x2B
#define QIB_7322_DebugPortNibbleSel_NibbleSel10_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel9_LSB 0x24
#define QIB_7322_DebugPortNibbleSel_NibbleSel9_MSB 0x27
#define QIB_7322_DebugPortNibbleSel_NibbleSel9_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel8_LSB 0x20
#define QIB_7322_DebugPortNibbleSel_NibbleSel8_MSB 0x23
#define QIB_7322_DebugPortNibbleSel_NibbleSel8_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel7_LSB 0x1C
#define QIB_7322_DebugPortNibbleSel_NibbleSel7_MSB 0x1F
#define QIB_7322_DebugPortNibbleSel_NibbleSel7_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel6_LSB 0x18
#define QIB_7322_DebugPortNibbleSel_NibbleSel6_MSB 0x1B
#define QIB_7322_DebugPortNibbleSel_NibbleSel6_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel5_LSB 0x14
#define QIB_7322_DebugPortNibbleSel_NibbleSel5_MSB 0x17
#define QIB_7322_DebugPortNibbleSel_NibbleSel5_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel4_LSB 0x10
#define QIB_7322_DebugPortNibbleSel_NibbleSel4_MSB 0x13
#define QIB_7322_DebugPortNibbleSel_NibbleSel4_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel3_LSB 0xC
#define QIB_7322_DebugPortNibbleSel_NibbleSel3_MSB 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel3_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel2_LSB 0x8
#define QIB_7322_DebugPortNibbleSel_NibbleSel2_MSB 0xB
#define QIB_7322_DebugPortNibbleSel_NibbleSel2_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel1_LSB 0x4
#define QIB_7322_DebugPortNibbleSel_NibbleSel1_MSB 0x7
#define QIB_7322_DebugPortNibbleSel_NibbleSel1_RMASK 0xF
#define QIB_7322_DebugPortNibbleSel_NibbleSel0_LSB 0x0
#define QIB_7322_DebugPortNibbleSel_NibbleSel0_MSB 0x3
#define QIB_7322_DebugPortNibbleSel_NibbleSel0_RMASK 0xF

#define QIB_7322_DebugSigsIntSel_OFFS 0x50
#define QIB_7322_DebugSigsIntSel_DEF 0x0000000000000000
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_b_1_LSB 0x31
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_b_1_MSB 0x33
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_b_1_RMASK 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_a_1_LSB 0x2E
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_a_1_MSB 0x30
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_a_1_RMASK 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_xgxs_1_LSB 0x2A
#define QIB_7322_DebugSigsIntSel_debug_port_sel_xgxs_1_MSB 0x2D
#define QIB_7322_DebugSigsIntSel_debug_port_sel_xgxs_1_RMASK 0xF
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_b_0_LSB 0x27
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_b_0_MSB 0x29
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_b_0_RMASK 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_a_0_LSB 0x24
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_a_0_MSB 0x26
#define QIB_7322_DebugSigsIntSel_debug_port_sel_credit_a_0_RMASK 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_xgxs_0_LSB 0x20
#define QIB_7322_DebugSigsIntSel_debug_port_sel_xgxs_0_MSB 0x23
#define QIB_7322_DebugSigsIntSel_debug_port_sel_xgxs_0_RMASK 0xF
#define QIB_7322_DebugSigsIntSel_debug_port_sel_rx_ibport_LSB 0x13
#define QIB_7322_DebugSigsIntSel_debug_port_sel_rx_ibport_MSB 0x13
#define QIB_7322_DebugSigsIntSel_debug_port_sel_rx_ibport_RMASK 0x1
#define QIB_7322_DebugSigsIntSel_debug_port_sel_tx_sdma_LSB 0x12
#define QIB_7322_DebugSigsIntSel_debug_port_sel_tx_sdma_MSB 0x12
#define QIB_7322_DebugSigsIntSel_debug_port_sel_tx_sdma_RMASK 0x1
#define QIB_7322_DebugSigsIntSel_debug_port_sel_tx_ibport_LSB 0x11
#define QIB_7322_DebugSigsIntSel_debug_port_sel_tx_ibport_MSB 0x11
#define QIB_7322_DebugSigsIntSel_debug_port_sel_tx_ibport_RMASK 0x1
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcie_rx_tx_LSB 0xF
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcie_rx_tx_MSB 0xF
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcie_rx_tx_RMASK 0x1
#define QIB_7322_DebugSigsIntSel_EnableSDma_SelfDrain_LSB 0xE
#define QIB_7322_DebugSigsIntSel_EnableSDma_SelfDrain_MSB 0xE
#define QIB_7322_DebugSigsIntSel_EnableSDma_SelfDrain_RMASK 0x1
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_rxdet_encdec_lane_LSB 0xB
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_rxdet_encdec_lane_MSB 0xD
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_rxdet_encdec_lane_RMASK 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_symlock_elfifo_lane_LSB 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_symlock_elfifo_lane_MSB 0xA
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_symlock_elfifo_lane_RMASK 0xF
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_sdout_LSB 0x6
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_sdout_MSB 0x6
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_sdout_RMASK 0x1
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_pipe_lane815_LSB 0x3
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_pipe_lane815_MSB 0x5
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_pipe_lane815_RMASK 0x7
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_pipe_lane07_LSB 0x0
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_pipe_lane07_MSB 0x2
#define QIB_7322_DebugSigsIntSel_debug_port_sel_pcs_pipe_lane07_RMASK 0x7

#define QIB_7322_DebugPortValueReg_OFFS 0x58

#define QIB_7322_IntBlocked_OFFS 0x60
#define QIB_7322_IntBlocked_DEF 0x0000000000000000
#define QIB_7322_IntBlocked_SDmaIntBlocked_1_LSB 0x3F
#define QIB_7322_IntBlocked_SDmaIntBlocked_1_MSB 0x3F
#define QIB_7322_IntBlocked_SDmaIntBlocked_1_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaIntBlocked_0_LSB 0x3E
#define QIB_7322_IntBlocked_SDmaIntBlocked_0_MSB 0x3E
#define QIB_7322_IntBlocked_SDmaIntBlocked_0_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaProgressIntBlocked_1_LSB 0x3D
#define QIB_7322_IntBlocked_SDmaProgressIntBlocked_1_MSB 0x3D
#define QIB_7322_IntBlocked_SDmaProgressIntBlocked_1_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaProgressIntBlocked_0_LSB 0x3C
#define QIB_7322_IntBlocked_SDmaProgressIntBlocked_0_MSB 0x3C
#define QIB_7322_IntBlocked_SDmaProgressIntBlocked_0_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaIdleIntBlocked_1_LSB 0x3B
#define QIB_7322_IntBlocked_SDmaIdleIntBlocked_1_MSB 0x3B
#define QIB_7322_IntBlocked_SDmaIdleIntBlocked_1_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaIdleIntBlocked_0_LSB 0x3A
#define QIB_7322_IntBlocked_SDmaIdleIntBlocked_0_MSB 0x3A
#define QIB_7322_IntBlocked_SDmaIdleIntBlocked_0_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaCleanupDoneBlocked_1_LSB 0x39
#define QIB_7322_IntBlocked_SDmaCleanupDoneBlocked_1_MSB 0x39
#define QIB_7322_IntBlocked_SDmaCleanupDoneBlocked_1_RMASK 0x1
#define QIB_7322_IntBlocked_SDmaCleanupDoneBlocked_0_LSB 0x38
#define QIB_7322_IntBlocked_SDmaCleanupDoneBlocked_0_MSB 0x38
#define QIB_7322_IntBlocked_SDmaCleanupDoneBlocked_0_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg17IntBlocked_LSB 0x31
#define QIB_7322_IntBlocked_RcvUrg17IntBlocked_MSB 0x31
#define QIB_7322_IntBlocked_RcvUrg17IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg16IntBlocked_LSB 0x30
#define QIB_7322_IntBlocked_RcvUrg16IntBlocked_MSB 0x30
#define QIB_7322_IntBlocked_RcvUrg16IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg15IntBlocked_LSB 0x2F
#define QIB_7322_IntBlocked_RcvUrg15IntBlocked_MSB 0x2F
#define QIB_7322_IntBlocked_RcvUrg15IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg14IntBlocked_LSB 0x2E
#define QIB_7322_IntBlocked_RcvUrg14IntBlocked_MSB 0x2E
#define QIB_7322_IntBlocked_RcvUrg14IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg13IntBlocked_LSB 0x2D
#define QIB_7322_IntBlocked_RcvUrg13IntBlocked_MSB 0x2D
#define QIB_7322_IntBlocked_RcvUrg13IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg12IntBlocked_LSB 0x2C
#define QIB_7322_IntBlocked_RcvUrg12IntBlocked_MSB 0x2C
#define QIB_7322_IntBlocked_RcvUrg12IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg11IntBlocked_LSB 0x2B
#define QIB_7322_IntBlocked_RcvUrg11IntBlocked_MSB 0x2B
#define QIB_7322_IntBlocked_RcvUrg11IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg10IntBlocked_LSB 0x2A
#define QIB_7322_IntBlocked_RcvUrg10IntBlocked_MSB 0x2A
#define QIB_7322_IntBlocked_RcvUrg10IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg9IntBlocked_LSB 0x29
#define QIB_7322_IntBlocked_RcvUrg9IntBlocked_MSB 0x29
#define QIB_7322_IntBlocked_RcvUrg9IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg8IntBlocked_LSB 0x28
#define QIB_7322_IntBlocked_RcvUrg8IntBlocked_MSB 0x28
#define QIB_7322_IntBlocked_RcvUrg8IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg7IntBlocked_LSB 0x27
#define QIB_7322_IntBlocked_RcvUrg7IntBlocked_MSB 0x27
#define QIB_7322_IntBlocked_RcvUrg7IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg6IntBlocked_LSB 0x26
#define QIB_7322_IntBlocked_RcvUrg6IntBlocked_MSB 0x26
#define QIB_7322_IntBlocked_RcvUrg6IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg5IntBlocked_LSB 0x25
#define QIB_7322_IntBlocked_RcvUrg5IntBlocked_MSB 0x25
#define QIB_7322_IntBlocked_RcvUrg5IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg4IntBlocked_LSB 0x24
#define QIB_7322_IntBlocked_RcvUrg4IntBlocked_MSB 0x24
#define QIB_7322_IntBlocked_RcvUrg4IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg3IntBlocked_LSB 0x23
#define QIB_7322_IntBlocked_RcvUrg3IntBlocked_MSB 0x23
#define QIB_7322_IntBlocked_RcvUrg3IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg2IntBlocked_LSB 0x22
#define QIB_7322_IntBlocked_RcvUrg2IntBlocked_MSB 0x22
#define QIB_7322_IntBlocked_RcvUrg2IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg1IntBlocked_LSB 0x21
#define QIB_7322_IntBlocked_RcvUrg1IntBlocked_MSB 0x21
#define QIB_7322_IntBlocked_RcvUrg1IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvUrg0IntBlocked_LSB 0x20
#define QIB_7322_IntBlocked_RcvUrg0IntBlocked_MSB 0x20
#define QIB_7322_IntBlocked_RcvUrg0IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_ErrIntBlocked_1_LSB 0x1F
#define QIB_7322_IntBlocked_ErrIntBlocked_1_MSB 0x1F
#define QIB_7322_IntBlocked_ErrIntBlocked_1_RMASK 0x1
#define QIB_7322_IntBlocked_ErrIntBlocked_0_LSB 0x1E
#define QIB_7322_IntBlocked_ErrIntBlocked_0_MSB 0x1E
#define QIB_7322_IntBlocked_ErrIntBlocked_0_RMASK 0x1
#define QIB_7322_IntBlocked_ErrIntBlocked_LSB 0x1D
#define QIB_7322_IntBlocked_ErrIntBlocked_MSB 0x1D
#define QIB_7322_IntBlocked_ErrIntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_AssertGPIOIntBlocked_LSB 0x1C
#define QIB_7322_IntBlocked_AssertGPIOIntBlocked_MSB 0x1C
#define QIB_7322_IntBlocked_AssertGPIOIntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_SendDoneIntBlocked_1_LSB 0x19
#define QIB_7322_IntBlocked_SendDoneIntBlocked_1_MSB 0x19
#define QIB_7322_IntBlocked_SendDoneIntBlocked_1_RMASK 0x1
#define QIB_7322_IntBlocked_SendDoneIntBlocked_0_LSB 0x18
#define QIB_7322_IntBlocked_SendDoneIntBlocked_0_MSB 0x18
#define QIB_7322_IntBlocked_SendDoneIntBlocked_0_RMASK 0x1
#define QIB_7322_IntBlocked_SendBufAvailIntBlocked_LSB 0x17
#define QIB_7322_IntBlocked_SendBufAvailIntBlocked_MSB 0x17
#define QIB_7322_IntBlocked_SendBufAvailIntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail17IntBlocked_LSB 0x11
#define QIB_7322_IntBlocked_RcvAvail17IntBlocked_MSB 0x11
#define QIB_7322_IntBlocked_RcvAvail17IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail16IntBlocked_LSB 0x10
#define QIB_7322_IntBlocked_RcvAvail16IntBlocked_MSB 0x10
#define QIB_7322_IntBlocked_RcvAvail16IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail15IntBlocked_LSB 0xF
#define QIB_7322_IntBlocked_RcvAvail15IntBlocked_MSB 0xF
#define QIB_7322_IntBlocked_RcvAvail15IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail14IntBlocked_LSB 0xE
#define QIB_7322_IntBlocked_RcvAvail14IntBlocked_MSB 0xE
#define QIB_7322_IntBlocked_RcvAvail14IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail13IntBlocked_LSB 0xD
#define QIB_7322_IntBlocked_RcvAvail13IntBlocked_MSB 0xD
#define QIB_7322_IntBlocked_RcvAvail13IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail12IntBlocked_LSB 0xC
#define QIB_7322_IntBlocked_RcvAvail12IntBlocked_MSB 0xC
#define QIB_7322_IntBlocked_RcvAvail12IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail11IntBlocked_LSB 0xB
#define QIB_7322_IntBlocked_RcvAvail11IntBlocked_MSB 0xB
#define QIB_7322_IntBlocked_RcvAvail11IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail10IntBlocked_LSB 0xA
#define QIB_7322_IntBlocked_RcvAvail10IntBlocked_MSB 0xA
#define QIB_7322_IntBlocked_RcvAvail10IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail9IntBlocked_LSB 0x9
#define QIB_7322_IntBlocked_RcvAvail9IntBlocked_MSB 0x9
#define QIB_7322_IntBlocked_RcvAvail9IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail8IntBlocked_LSB 0x8
#define QIB_7322_IntBlocked_RcvAvail8IntBlocked_MSB 0x8
#define QIB_7322_IntBlocked_RcvAvail8IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail7IntBlocked_LSB 0x7
#define QIB_7322_IntBlocked_RcvAvail7IntBlocked_MSB 0x7
#define QIB_7322_IntBlocked_RcvAvail7IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail6IntBlocked_LSB 0x6
#define QIB_7322_IntBlocked_RcvAvail6IntBlocked_MSB 0x6
#define QIB_7322_IntBlocked_RcvAvail6IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail5IntBlocked_LSB 0x5
#define QIB_7322_IntBlocked_RcvAvail5IntBlocked_MSB 0x5
#define QIB_7322_IntBlocked_RcvAvail5IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail4IntBlocked_LSB 0x4
#define QIB_7322_IntBlocked_RcvAvail4IntBlocked_MSB 0x4
#define QIB_7322_IntBlocked_RcvAvail4IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail3IntBlocked_LSB 0x3
#define QIB_7322_IntBlocked_RcvAvail3IntBlocked_MSB 0x3
#define QIB_7322_IntBlocked_RcvAvail3IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail2IntBlocked_LSB 0x2
#define QIB_7322_IntBlocked_RcvAvail2IntBlocked_MSB 0x2
#define QIB_7322_IntBlocked_RcvAvail2IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail1IntBlocked_LSB 0x1
#define QIB_7322_IntBlocked_RcvAvail1IntBlocked_MSB 0x1
#define QIB_7322_IntBlocked_RcvAvail1IntBlocked_RMASK 0x1
#define QIB_7322_IntBlocked_RcvAvail0IntBlocked_LSB 0x0
#define QIB_7322_IntBlocked_RcvAvail0IntBlocked_MSB 0x0
#define QIB_7322_IntBlocked_RcvAvail0IntBlocked_RMASK 0x1

#define QIB_7322_IntMask_OFFS 0x68
#define QIB_7322_IntMask_DEF 0x0000000000000000
#define QIB_7322_IntMask_SDmaIntMask_1_LSB 0x3F
#define QIB_7322_IntMask_SDmaIntMask_1_MSB 0x3F
#define QIB_7322_IntMask_SDmaIntMask_1_RMASK 0x1
#define QIB_7322_IntMask_SDmaIntMask_0_LSB 0x3E
#define QIB_7322_IntMask_SDmaIntMask_0_MSB 0x3E
#define QIB_7322_IntMask_SDmaIntMask_0_RMASK 0x1
#define QIB_7322_IntMask_SDmaProgressIntMask_1_LSB 0x3D
#define QIB_7322_IntMask_SDmaProgressIntMask_1_MSB 0x3D
#define QIB_7322_IntMask_SDmaProgressIntMask_1_RMASK 0x1
#define QIB_7322_IntMask_SDmaProgressIntMask_0_LSB 0x3C
#define QIB_7322_IntMask_SDmaProgressIntMask_0_MSB 0x3C
#define QIB_7322_IntMask_SDmaProgressIntMask_0_RMASK 0x1
#define QIB_7322_IntMask_SDmaIdleIntMask_1_LSB 0x3B
#define QIB_7322_IntMask_SDmaIdleIntMask_1_MSB 0x3B
#define QIB_7322_IntMask_SDmaIdleIntMask_1_RMASK 0x1
#define QIB_7322_IntMask_SDmaIdleIntMask_0_LSB 0x3A
#define QIB_7322_IntMask_SDmaIdleIntMask_0_MSB 0x3A
#define QIB_7322_IntMask_SDmaIdleIntMask_0_RMASK 0x1
#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_LSB 0x39
#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_MSB 0x39
#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_RMASK 0x1
#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_LSB 0x38
#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_MSB 0x38
#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg17IntMask_LSB 0x31
#define QIB_7322_IntMask_RcvUrg17IntMask_MSB 0x31
#define QIB_7322_IntMask_RcvUrg17IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg16IntMask_LSB 0x30
#define QIB_7322_IntMask_RcvUrg16IntMask_MSB 0x30
#define QIB_7322_IntMask_RcvUrg16IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg15IntMask_LSB 0x2F
#define QIB_7322_IntMask_RcvUrg15IntMask_MSB 0x2F
#define QIB_7322_IntMask_RcvUrg15IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg14IntMask_LSB 0x2E
#define QIB_7322_IntMask_RcvUrg14IntMask_MSB 0x2E
#define QIB_7322_IntMask_RcvUrg14IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg13IntMask_LSB 0x2D
#define QIB_7322_IntMask_RcvUrg13IntMask_MSB 0x2D
#define QIB_7322_IntMask_RcvUrg13IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg12IntMask_LSB 0x2C
#define QIB_7322_IntMask_RcvUrg12IntMask_MSB 0x2C
#define QIB_7322_IntMask_RcvUrg12IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg11IntMask_LSB 0x2B
#define QIB_7322_IntMask_RcvUrg11IntMask_MSB 0x2B
#define QIB_7322_IntMask_RcvUrg11IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg10IntMask_LSB 0x2A
#define QIB_7322_IntMask_RcvUrg10IntMask_MSB 0x2A
#define QIB_7322_IntMask_RcvUrg10IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg9IntMask_LSB 0x29
#define QIB_7322_IntMask_RcvUrg9IntMask_MSB 0x29
#define QIB_7322_IntMask_RcvUrg9IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg8IntMask_LSB 0x28
#define QIB_7322_IntMask_RcvUrg8IntMask_MSB 0x28
#define QIB_7322_IntMask_RcvUrg8IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg7IntMask_LSB 0x27
#define QIB_7322_IntMask_RcvUrg7IntMask_MSB 0x27
#define QIB_7322_IntMask_RcvUrg7IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg6IntMask_LSB 0x26
#define QIB_7322_IntMask_RcvUrg6IntMask_MSB 0x26
#define QIB_7322_IntMask_RcvUrg6IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg5IntMask_LSB 0x25
#define QIB_7322_IntMask_RcvUrg5IntMask_MSB 0x25
#define QIB_7322_IntMask_RcvUrg5IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg4IntMask_LSB 0x24
#define QIB_7322_IntMask_RcvUrg4IntMask_MSB 0x24
#define QIB_7322_IntMask_RcvUrg4IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg3IntMask_LSB 0x23
#define QIB_7322_IntMask_RcvUrg3IntMask_MSB 0x23
#define QIB_7322_IntMask_RcvUrg3IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg2IntMask_LSB 0x22
#define QIB_7322_IntMask_RcvUrg2IntMask_MSB 0x22
#define QIB_7322_IntMask_RcvUrg2IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg1IntMask_LSB 0x21
#define QIB_7322_IntMask_RcvUrg1IntMask_MSB 0x21
#define QIB_7322_IntMask_RcvUrg1IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvUrg0IntMask_LSB 0x20
#define QIB_7322_IntMask_RcvUrg0IntMask_MSB 0x20
#define QIB_7322_IntMask_RcvUrg0IntMask_RMASK 0x1
#define QIB_7322_IntMask_ErrIntMask_1_LSB 0x1F
#define QIB_7322_IntMask_ErrIntMask_1_MSB 0x1F
#define QIB_7322_IntMask_ErrIntMask_1_RMASK 0x1
#define QIB_7322_IntMask_ErrIntMask_0_LSB 0x1E
#define QIB_7322_IntMask_ErrIntMask_0_MSB 0x1E
#define QIB_7322_IntMask_ErrIntMask_0_RMASK 0x1
#define QIB_7322_IntMask_ErrIntMask_LSB 0x1D
#define QIB_7322_IntMask_ErrIntMask_MSB 0x1D
#define QIB_7322_IntMask_ErrIntMask_RMASK 0x1
#define QIB_7322_IntMask_AssertGPIOIntMask_LSB 0x1C
#define QIB_7322_IntMask_AssertGPIOIntMask_MSB 0x1C
#define QIB_7322_IntMask_AssertGPIOIntMask_RMASK 0x1
#define QIB_7322_IntMask_SendDoneIntMask_1_LSB 0x19
#define QIB_7322_IntMask_SendDoneIntMask_1_MSB 0x19
#define QIB_7322_IntMask_SendDoneIntMask_1_RMASK 0x1
#define QIB_7322_IntMask_SendDoneIntMask_0_LSB 0x18
#define QIB_7322_IntMask_SendDoneIntMask_0_MSB 0x18
#define QIB_7322_IntMask_SendDoneIntMask_0_RMASK 0x1
#define QIB_7322_IntMask_SendBufAvailIntMask_LSB 0x17
#define QIB_7322_IntMask_SendBufAvailIntMask_MSB 0x17
#define QIB_7322_IntMask_SendBufAvailIntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail17IntMask_LSB 0x11
#define QIB_7322_IntMask_RcvAvail17IntMask_MSB 0x11
#define QIB_7322_IntMask_RcvAvail17IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail16IntMask_LSB 0x10
#define QIB_7322_IntMask_RcvAvail16IntMask_MSB 0x10
#define QIB_7322_IntMask_RcvAvail16IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail15IntMask_LSB 0xF
#define QIB_7322_IntMask_RcvAvail15IntMask_MSB 0xF
#define QIB_7322_IntMask_RcvAvail15IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail14IntMask_LSB 0xE
#define QIB_7322_IntMask_RcvAvail14IntMask_MSB 0xE
#define QIB_7322_IntMask_RcvAvail14IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail13IntMask_LSB 0xD
#define QIB_7322_IntMask_RcvAvail13IntMask_MSB 0xD
#define QIB_7322_IntMask_RcvAvail13IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail12IntMask_LSB 0xC
#define QIB_7322_IntMask_RcvAvail12IntMask_MSB 0xC
#define QIB_7322_IntMask_RcvAvail12IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail11IntMask_LSB 0xB
#define QIB_7322_IntMask_RcvAvail11IntMask_MSB 0xB
#define QIB_7322_IntMask_RcvAvail11IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail10IntMask_LSB 0xA
#define QIB_7322_IntMask_RcvAvail10IntMask_MSB 0xA
#define QIB_7322_IntMask_RcvAvail10IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail9IntMask_LSB 0x9
#define QIB_7322_IntMask_RcvAvail9IntMask_MSB 0x9
#define QIB_7322_IntMask_RcvAvail9IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail8IntMask_LSB 0x8
#define QIB_7322_IntMask_RcvAvail8IntMask_MSB 0x8
#define QIB_7322_IntMask_RcvAvail8IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail7IntMask_LSB 0x7
#define QIB_7322_IntMask_RcvAvail7IntMask_MSB 0x7
#define QIB_7322_IntMask_RcvAvail7IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail6IntMask_LSB 0x6
#define QIB_7322_IntMask_RcvAvail6IntMask_MSB 0x6
#define QIB_7322_IntMask_RcvAvail6IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail5IntMask_LSB 0x5
#define QIB_7322_IntMask_RcvAvail5IntMask_MSB 0x5
#define QIB_7322_IntMask_RcvAvail5IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail4IntMask_LSB 0x4
#define QIB_7322_IntMask_RcvAvail4IntMask_MSB 0x4
#define QIB_7322_IntMask_RcvAvail4IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail3IntMask_LSB 0x3
#define QIB_7322_IntMask_RcvAvail3IntMask_MSB 0x3
#define QIB_7322_IntMask_RcvAvail3IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail2IntMask_LSB 0x2
#define QIB_7322_IntMask_RcvAvail2IntMask_MSB 0x2
#define QIB_7322_IntMask_RcvAvail2IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail1IntMask_LSB 0x1
#define QIB_7322_IntMask_RcvAvail1IntMask_MSB 0x1
#define QIB_7322_IntMask_RcvAvail1IntMask_RMASK 0x1
#define QIB_7322_IntMask_RcvAvail0IntMask_LSB 0x0
#define QIB_7322_IntMask_RcvAvail0IntMask_MSB 0x0
#define QIB_7322_IntMask_RcvAvail0IntMask_RMASK 0x1

#define QIB_7322_IntStatus_OFFS 0x70
#define QIB_7322_IntStatus_DEF 0x0000000000000000
#define QIB_7322_IntStatus_SDmaInt_1_LSB 0x3F
#define QIB_7322_IntStatus_SDmaInt_1_MSB 0x3F
#define QIB_7322_IntStatus_SDmaInt_1_RMASK 0x1
#define QIB_7322_IntStatus_SDmaInt_0_LSB 0x3E
#define QIB_7322_IntStatus_SDmaInt_0_MSB 0x3E
#define QIB_7322_IntStatus_SDmaInt_0_RMASK 0x1
#define QIB_7322_IntStatus_SDmaProgressInt_1_LSB 0x3D
#define QIB_7322_IntStatus_SDmaProgressInt_1_MSB 0x3D
#define QIB_7322_IntStatus_SDmaProgressInt_1_RMASK 0x1
#define QIB_7322_IntStatus_SDmaProgressInt_0_LSB 0x3C
#define QIB_7322_IntStatus_SDmaProgressInt_0_MSB 0x3C
#define QIB_7322_IntStatus_SDmaProgressInt_0_RMASK 0x1
#define QIB_7322_IntStatus_SDmaIdleInt_1_LSB 0x3B
#define QIB_7322_IntStatus_SDmaIdleInt_1_MSB 0x3B
#define QIB_7322_IntStatus_SDmaIdleInt_1_RMASK 0x1
#define QIB_7322_IntStatus_SDmaIdleInt_0_LSB 0x3A
#define QIB_7322_IntStatus_SDmaIdleInt_0_MSB 0x3A
#define QIB_7322_IntStatus_SDmaIdleInt_0_RMASK 0x1
#define QIB_7322_IntStatus_SDmaCleanupDone_1_LSB 0x39
#define QIB_7322_IntStatus_SDmaCleanupDone_1_MSB 0x39
#define QIB_7322_IntStatus_SDmaCleanupDone_1_RMASK 0x1
#define QIB_7322_IntStatus_SDmaCleanupDone_0_LSB 0x38
#define QIB_7322_IntStatus_SDmaCleanupDone_0_MSB 0x38
#define QIB_7322_IntStatus_SDmaCleanupDone_0_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg17_LSB 0x31
#define QIB_7322_IntStatus_RcvUrg17_MSB 0x31
#define QIB_7322_IntStatus_RcvUrg17_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg16_LSB 0x30
#define QIB_7322_IntStatus_RcvUrg16_MSB 0x30
#define QIB_7322_IntStatus_RcvUrg16_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg15_LSB 0x2F
#define QIB_7322_IntStatus_RcvUrg15_MSB 0x2F
#define QIB_7322_IntStatus_RcvUrg15_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg14_LSB 0x2E
#define QIB_7322_IntStatus_RcvUrg14_MSB 0x2E
#define QIB_7322_IntStatus_RcvUrg14_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg13_LSB 0x2D
#define QIB_7322_IntStatus_RcvUrg13_MSB 0x2D
#define QIB_7322_IntStatus_RcvUrg13_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg12_LSB 0x2C
#define QIB_7322_IntStatus_RcvUrg12_MSB 0x2C
#define QIB_7322_IntStatus_RcvUrg12_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg11_LSB 0x2B
#define QIB_7322_IntStatus_RcvUrg11_MSB 0x2B
#define QIB_7322_IntStatus_RcvUrg11_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg10_LSB 0x2A
#define QIB_7322_IntStatus_RcvUrg10_MSB 0x2A
#define QIB_7322_IntStatus_RcvUrg10_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg9_LSB 0x29
#define QIB_7322_IntStatus_RcvUrg9_MSB 0x29
#define QIB_7322_IntStatus_RcvUrg9_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg8_LSB 0x28
#define QIB_7322_IntStatus_RcvUrg8_MSB 0x28
#define QIB_7322_IntStatus_RcvUrg8_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg7_LSB 0x27
#define QIB_7322_IntStatus_RcvUrg7_MSB 0x27
#define QIB_7322_IntStatus_RcvUrg7_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg6_LSB 0x26
#define QIB_7322_IntStatus_RcvUrg6_MSB 0x26
#define QIB_7322_IntStatus_RcvUrg6_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg5_LSB 0x25
#define QIB_7322_IntStatus_RcvUrg5_MSB 0x25
#define QIB_7322_IntStatus_RcvUrg5_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg4_LSB 0x24
#define QIB_7322_IntStatus_RcvUrg4_MSB 0x24
#define QIB_7322_IntStatus_RcvUrg4_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg3_LSB 0x23
#define QIB_7322_IntStatus_RcvUrg3_MSB 0x23
#define QIB_7322_IntStatus_RcvUrg3_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg2_LSB 0x22
#define QIB_7322_IntStatus_RcvUrg2_MSB 0x22
#define QIB_7322_IntStatus_RcvUrg2_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg1_LSB 0x21
#define QIB_7322_IntStatus_RcvUrg1_MSB 0x21
#define QIB_7322_IntStatus_RcvUrg1_RMASK 0x1
#define QIB_7322_IntStatus_RcvUrg0_LSB 0x20
#define QIB_7322_IntStatus_RcvUrg0_MSB 0x20
#define QIB_7322_IntStatus_RcvUrg0_RMASK 0x1
#define QIB_7322_IntStatus_Err_1_LSB 0x1F
#define QIB_7322_IntStatus_Err_1_MSB 0x1F
#define QIB_7322_IntStatus_Err_1_RMASK 0x1
#define QIB_7322_IntStatus_Err_0_LSB 0x1E
#define QIB_7322_IntStatus_Err_0_MSB 0x1E
#define QIB_7322_IntStatus_Err_0_RMASK 0x1
#define QIB_7322_IntStatus_Err_LSB 0x1D
#define QIB_7322_IntStatus_Err_MSB 0x1D
#define QIB_7322_IntStatus_Err_RMASK 0x1
#define QIB_7322_IntStatus_AssertGPIO_LSB 0x1C
#define QIB_7322_IntStatus_AssertGPIO_MSB 0x1C
#define QIB_7322_IntStatus_AssertGPIO_RMASK 0x1
#define QIB_7322_IntStatus_SendDone_1_LSB 0x19
#define QIB_7322_IntStatus_SendDone_1_MSB 0x19
#define QIB_7322_IntStatus_SendDone_1_RMASK 0x1
#define QIB_7322_IntStatus_SendDone_0_LSB 0x18
#define QIB_7322_IntStatus_SendDone_0_MSB 0x18
#define QIB_7322_IntStatus_SendDone_0_RMASK 0x1
#define QIB_7322_IntStatus_SendBufAvail_LSB 0x17
#define QIB_7322_IntStatus_SendBufAvail_MSB 0x17
#define QIB_7322_IntStatus_SendBufAvail_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail17_LSB 0x11
#define QIB_7322_IntStatus_RcvAvail17_MSB 0x11
#define QIB_7322_IntStatus_RcvAvail17_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail16_LSB 0x10
#define QIB_7322_IntStatus_RcvAvail16_MSB 0x10
#define QIB_7322_IntStatus_RcvAvail16_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail15_LSB 0xF
#define QIB_7322_IntStatus_RcvAvail15_MSB 0xF
#define QIB_7322_IntStatus_RcvAvail15_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail14_LSB 0xE
#define QIB_7322_IntStatus_RcvAvail14_MSB 0xE
#define QIB_7322_IntStatus_RcvAvail14_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail13_LSB 0xD
#define QIB_7322_IntStatus_RcvAvail13_MSB 0xD
#define QIB_7322_IntStatus_RcvAvail13_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail12_LSB 0xC
#define QIB_7322_IntStatus_RcvAvail12_MSB 0xC
#define QIB_7322_IntStatus_RcvAvail12_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail11_LSB 0xB
#define QIB_7322_IntStatus_RcvAvail11_MSB 0xB
#define QIB_7322_IntStatus_RcvAvail11_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail10_LSB 0xA
#define QIB_7322_IntStatus_RcvAvail10_MSB 0xA
#define QIB_7322_IntStatus_RcvAvail10_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail9_LSB 0x9
#define QIB_7322_IntStatus_RcvAvail9_MSB 0x9
#define QIB_7322_IntStatus_RcvAvail9_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail8_LSB 0x8
#define QIB_7322_IntStatus_RcvAvail8_MSB 0x8
#define QIB_7322_IntStatus_RcvAvail8_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail7_LSB 0x7
#define QIB_7322_IntStatus_RcvAvail7_MSB 0x7
#define QIB_7322_IntStatus_RcvAvail7_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail6_LSB 0x6
#define QIB_7322_IntStatus_RcvAvail6_MSB 0x6
#define QIB_7322_IntStatus_RcvAvail6_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail5_LSB 0x5
#define QIB_7322_IntStatus_RcvAvail5_MSB 0x5
#define QIB_7322_IntStatus_RcvAvail5_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail4_LSB 0x4
#define QIB_7322_IntStatus_RcvAvail4_MSB 0x4
#define QIB_7322_IntStatus_RcvAvail4_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail3_LSB 0x3
#define QIB_7322_IntStatus_RcvAvail3_MSB 0x3
#define QIB_7322_IntStatus_RcvAvail3_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail2_LSB 0x2
#define QIB_7322_IntStatus_RcvAvail2_MSB 0x2
#define QIB_7322_IntStatus_RcvAvail2_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail1_LSB 0x1
#define QIB_7322_IntStatus_RcvAvail1_MSB 0x1
#define QIB_7322_IntStatus_RcvAvail1_RMASK 0x1
#define QIB_7322_IntStatus_RcvAvail0_LSB 0x0
#define QIB_7322_IntStatus_RcvAvail0_MSB 0x0
#define QIB_7322_IntStatus_RcvAvail0_RMASK 0x1

#define QIB_7322_IntClear_OFFS 0x78
#define QIB_7322_IntClear_DEF 0x0000000000000000
#define QIB_7322_IntClear_SDmaIntClear_1_LSB 0x3F
#define QIB_7322_IntClear_SDmaIntClear_1_MSB 0x3F
#define QIB_7322_IntClear_SDmaIntClear_1_RMASK 0x1
#define QIB_7322_IntClear_SDmaIntClear_0_LSB 0x3E
#define QIB_7322_IntClear_SDmaIntClear_0_MSB 0x3E
#define QIB_7322_IntClear_SDmaIntClear_0_RMASK 0x1
#define QIB_7322_IntClear_SDmaProgressIntClear_1_LSB 0x3D
#define QIB_7322_IntClear_SDmaProgressIntClear_1_MSB 0x3D
#define QIB_7322_IntClear_SDmaProgressIntClear_1_RMASK 0x1
#define QIB_7322_IntClear_SDmaProgressIntClear_0_LSB 0x3C
#define QIB_7322_IntClear_SDmaProgressIntClear_0_MSB 0x3C
#define QIB_7322_IntClear_SDmaProgressIntClear_0_RMASK 0x1
#define QIB_7322_IntClear_SDmaIdleIntClear_1_LSB 0x3B
#define QIB_7322_IntClear_SDmaIdleIntClear_1_MSB 0x3B
#define QIB_7322_IntClear_SDmaIdleIntClear_1_RMASK 0x1
#define QIB_7322_IntClear_SDmaIdleIntClear_0_LSB 0x3A
#define QIB_7322_IntClear_SDmaIdleIntClear_0_MSB 0x3A
#define QIB_7322_IntClear_SDmaIdleIntClear_0_RMASK 0x1
#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_LSB 0x39
#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_MSB 0x39
#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_RMASK 0x1
#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_LSB 0x38
#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_MSB 0x38
#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg17IntClear_LSB 0x31
#define QIB_7322_IntClear_RcvUrg17IntClear_MSB 0x31
#define QIB_7322_IntClear_RcvUrg17IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg16IntClear_LSB 0x30
#define QIB_7322_IntClear_RcvUrg16IntClear_MSB 0x30
#define QIB_7322_IntClear_RcvUrg16IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg15IntClear_LSB 0x2F
#define QIB_7322_IntClear_RcvUrg15IntClear_MSB 0x2F
#define QIB_7322_IntClear_RcvUrg15IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg14IntClear_LSB 0x2E
#define QIB_7322_IntClear_RcvUrg14IntClear_MSB 0x2E
#define QIB_7322_IntClear_RcvUrg14IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg13IntClear_LSB 0x2D
#define QIB_7322_IntClear_RcvUrg13IntClear_MSB 0x2D
#define QIB_7322_IntClear_RcvUrg13IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg12IntClear_LSB 0x2C
#define QIB_7322_IntClear_RcvUrg12IntClear_MSB 0x2C
#define QIB_7322_IntClear_RcvUrg12IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg11IntClear_LSB 0x2B
#define QIB_7322_IntClear_RcvUrg11IntClear_MSB 0x2B
#define QIB_7322_IntClear_RcvUrg11IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg10IntClear_LSB 0x2A
#define QIB_7322_IntClear_RcvUrg10IntClear_MSB 0x2A
#define QIB_7322_IntClear_RcvUrg10IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg9IntClear_LSB 0x29
#define QIB_7322_IntClear_RcvUrg9IntClear_MSB 0x29
#define QIB_7322_IntClear_RcvUrg9IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg8IntClear_LSB 0x28
#define QIB_7322_IntClear_RcvUrg8IntClear_MSB 0x28
#define QIB_7322_IntClear_RcvUrg8IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg7IntClear_LSB 0x27
#define QIB_7322_IntClear_RcvUrg7IntClear_MSB 0x27
#define QIB_7322_IntClear_RcvUrg7IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg6IntClear_LSB 0x26
#define QIB_7322_IntClear_RcvUrg6IntClear_MSB 0x26
#define QIB_7322_IntClear_RcvUrg6IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg5IntClear_LSB 0x25
#define QIB_7322_IntClear_RcvUrg5IntClear_MSB 0x25
#define QIB_7322_IntClear_RcvUrg5IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg4IntClear_LSB 0x24
#define QIB_7322_IntClear_RcvUrg4IntClear_MSB 0x24
#define QIB_7322_IntClear_RcvUrg4IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg3IntClear_LSB 0x23
#define QIB_7322_IntClear_RcvUrg3IntClear_MSB 0x23
#define QIB_7322_IntClear_RcvUrg3IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg2IntClear_LSB 0x22
#define QIB_7322_IntClear_RcvUrg2IntClear_MSB 0x22
#define QIB_7322_IntClear_RcvUrg2IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg1IntClear_LSB 0x21
#define QIB_7322_IntClear_RcvUrg1IntClear_MSB 0x21
#define QIB_7322_IntClear_RcvUrg1IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvUrg0IntClear_LSB 0x20
#define QIB_7322_IntClear_RcvUrg0IntClear_MSB 0x20
#define QIB_7322_IntClear_RcvUrg0IntClear_RMASK 0x1
#define QIB_7322_IntClear_ErrIntClear_1_LSB 0x1F
#define QIB_7322_IntClear_ErrIntClear_1_MSB 0x1F
#define QIB_7322_IntClear_ErrIntClear_1_RMASK 0x1
#define QIB_7322_IntClear_ErrIntClear_0_LSB 0x1E
#define QIB_7322_IntClear_ErrIntClear_0_MSB 0x1E
#define QIB_7322_IntClear_ErrIntClear_0_RMASK 0x1
#define QIB_7322_IntClear_ErrIntClear_LSB 0x1D
#define QIB_7322_IntClear_ErrIntClear_MSB 0x1D
#define QIB_7322_IntClear_ErrIntClear_RMASK 0x1
#define QIB_7322_IntClear_AssertGPIOIntClear_LSB 0x1C
#define QIB_7322_IntClear_AssertGPIOIntClear_MSB 0x1C
#define QIB_7322_IntClear_AssertGPIOIntClear_RMASK 0x1
#define QIB_7322_IntClear_SendDoneIntClear_1_LSB 0x19
#define QIB_7322_IntClear_SendDoneIntClear_1_MSB 0x19
#define QIB_7322_IntClear_SendDoneIntClear_1_RMASK 0x1
#define QIB_7322_IntClear_SendDoneIntClear_0_LSB 0x18
#define QIB_7322_IntClear_SendDoneIntClear_0_MSB 0x18
#define QIB_7322_IntClear_SendDoneIntClear_0_RMASK 0x1
#define QIB_7322_IntClear_SendBufAvailIntClear_LSB 0x17
#define QIB_7322_IntClear_SendBufAvailIntClear_MSB 0x17
#define QIB_7322_IntClear_SendBufAvailIntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail17IntClear_LSB 0x11
#define QIB_7322_IntClear_RcvAvail17IntClear_MSB 0x11
#define QIB_7322_IntClear_RcvAvail17IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail16IntClear_LSB 0x10
#define QIB_7322_IntClear_RcvAvail16IntClear_MSB 0x10
#define QIB_7322_IntClear_RcvAvail16IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail15IntClear_LSB 0xF
#define QIB_7322_IntClear_RcvAvail15IntClear_MSB 0xF
#define QIB_7322_IntClear_RcvAvail15IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail14IntClear_LSB 0xE
#define QIB_7322_IntClear_RcvAvail14IntClear_MSB 0xE
#define QIB_7322_IntClear_RcvAvail14IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail13IntClear_LSB 0xD
#define QIB_7322_IntClear_RcvAvail13IntClear_MSB 0xD
#define QIB_7322_IntClear_RcvAvail13IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail12IntClear_LSB 0xC
#define QIB_7322_IntClear_RcvAvail12IntClear_MSB 0xC
#define QIB_7322_IntClear_RcvAvail12IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail11IntClear_LSB 0xB
#define QIB_7322_IntClear_RcvAvail11IntClear_MSB 0xB
#define QIB_7322_IntClear_RcvAvail11IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail10IntClear_LSB 0xA
#define QIB_7322_IntClear_RcvAvail10IntClear_MSB 0xA
#define QIB_7322_IntClear_RcvAvail10IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail9IntClear_LSB 0x9
#define QIB_7322_IntClear_RcvAvail9IntClear_MSB 0x9
#define QIB_7322_IntClear_RcvAvail9IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail8IntClear_LSB 0x8
#define QIB_7322_IntClear_RcvAvail8IntClear_MSB 0x8
#define QIB_7322_IntClear_RcvAvail8IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail7IntClear_LSB 0x7
#define QIB_7322_IntClear_RcvAvail7IntClear_MSB 0x7
#define QIB_7322_IntClear_RcvAvail7IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail6IntClear_LSB 0x6
#define QIB_7322_IntClear_RcvAvail6IntClear_MSB 0x6
#define QIB_7322_IntClear_RcvAvail6IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail5IntClear_LSB 0x5
#define QIB_7322_IntClear_RcvAvail5IntClear_MSB 0x5
#define QIB_7322_IntClear_RcvAvail5IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail4IntClear_LSB 0x4
#define QIB_7322_IntClear_RcvAvail4IntClear_MSB 0x4
#define QIB_7322_IntClear_RcvAvail4IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail3IntClear_LSB 0x3
#define QIB_7322_IntClear_RcvAvail3IntClear_MSB 0x3
#define QIB_7322_IntClear_RcvAvail3IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail2IntClear_LSB 0x2
#define QIB_7322_IntClear_RcvAvail2IntClear_MSB 0x2
#define QIB_7322_IntClear_RcvAvail2IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail1IntClear_LSB 0x1
#define QIB_7322_IntClear_RcvAvail1IntClear_MSB 0x1
#define QIB_7322_IntClear_RcvAvail1IntClear_RMASK 0x1
#define QIB_7322_IntClear_RcvAvail0IntClear_LSB 0x0
#define QIB_7322_IntClear_RcvAvail0IntClear_MSB 0x0
#define QIB_7322_IntClear_RcvAvail0IntClear_RMASK 0x1

#define QIB_7322_ErrMask_OFFS 0x80
#define QIB_7322_ErrMask_DEF 0x0000000000000000
#define QIB_7322_ErrMask_ResetNegatedMask_LSB 0x3F
#define QIB_7322_ErrMask_ResetNegatedMask_MSB 0x3F
#define QIB_7322_ErrMask_ResetNegatedMask_RMASK 0x1
#define QIB_7322_ErrMask_HardwareErrMask_LSB 0x3E
#define QIB_7322_ErrMask_HardwareErrMask_MSB 0x3E
#define QIB_7322_ErrMask_HardwareErrMask_RMASK 0x1
#define QIB_7322_ErrMask_InvalidAddrErrMask_LSB 0x3D
#define QIB_7322_ErrMask_InvalidAddrErrMask_MSB 0x3D
#define QIB_7322_ErrMask_InvalidAddrErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SDmaVL15ErrMask_LSB 0x38
#define QIB_7322_ErrMask_SDmaVL15ErrMask_MSB 0x38
#define QIB_7322_ErrMask_SDmaVL15ErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_LSB 0x37
#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_MSB 0x37
#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_InvalidEEPCmdMask_LSB 0x35
#define QIB_7322_ErrMask_InvalidEEPCmdMask_MSB 0x35
#define QIB_7322_ErrMask_InvalidEEPCmdMask_RMASK 0x1
#define QIB_7322_ErrMask_RcvContextShareErrMask_LSB 0x34
#define QIB_7322_ErrMask_RcvContextShareErrMask_MSB 0x34
#define QIB_7322_ErrMask_RcvContextShareErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SendVLMismatchErrMask_LSB 0x24
#define QIB_7322_ErrMask_SendVLMismatchErrMask_MSB 0x24
#define QIB_7322_ErrMask_SendVLMismatchErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SendArmLaunchErrMask_LSB 0x23
#define QIB_7322_ErrMask_SendArmLaunchErrMask_MSB 0x23
#define QIB_7322_ErrMask_SendArmLaunchErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_LSB 0x1B
#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_MSB 0x1B
#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SDmaWrongPortErrMask_LSB 0x1A
#define QIB_7322_ErrMask_SDmaWrongPortErrMask_MSB 0x1A
#define QIB_7322_ErrMask_SDmaWrongPortErrMask_RMASK 0x1
#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_LSB 0x19
#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_MSB 0x19
#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_RMASK 0x1
#define QIB_7322_ErrMask_RcvHdrFullErrMask_LSB 0xD
#define QIB_7322_ErrMask_RcvHdrFullErrMask_MSB 0xD
#define QIB_7322_ErrMask_RcvHdrFullErrMask_RMASK 0x1
#define QIB_7322_ErrMask_RcvEgrFullErrMask_LSB 0xC
#define QIB_7322_ErrMask_RcvEgrFullErrMask_MSB 0xC
#define QIB_7322_ErrMask_RcvEgrFullErrMask_RMASK 0x1

#define QIB_7322_ErrStatus_OFFS 0x88
#define QIB_7322_ErrStatus_DEF 0x0000000000000000
#define QIB_7322_ErrStatus_ResetNegated_LSB 0x3F
#define QIB_7322_ErrStatus_ResetNegated_MSB 0x3F
#define QIB_7322_ErrStatus_ResetNegated_RMASK 0x1
#define QIB_7322_ErrStatus_HardwareErr_LSB 0x3E
#define QIB_7322_ErrStatus_HardwareErr_MSB 0x3E
#define QIB_7322_ErrStatus_HardwareErr_RMASK 0x1
#define QIB_7322_ErrStatus_InvalidAddrErr_LSB 0x3D
#define QIB_7322_ErrStatus_InvalidAddrErr_MSB 0x3D
#define QIB_7322_ErrStatus_InvalidAddrErr_RMASK 0x1
#define QIB_7322_ErrStatus_SDmaVL15Err_LSB 0x38
#define QIB_7322_ErrStatus_SDmaVL15Err_MSB 0x38
#define QIB_7322_ErrStatus_SDmaVL15Err_RMASK 0x1
#define QIB_7322_ErrStatus_SBufVL15MisUseErr_LSB 0x37
#define QIB_7322_ErrStatus_SBufVL15MisUseErr_MSB 0x37
#define QIB_7322_ErrStatus_SBufVL15MisUseErr_RMASK 0x1
#define QIB_7322_ErrStatus_InvalidEEPCmdErr_LSB 0x35
#define QIB_7322_ErrStatus_InvalidEEPCmdErr_MSB 0x35
#define QIB_7322_ErrStatus_InvalidEEPCmdErr_RMASK 0x1
#define QIB_7322_ErrStatus_RcvContextShareErr_LSB 0x34
#define QIB_7322_ErrStatus_RcvContextShareErr_MSB 0x34
#define QIB_7322_ErrStatus_RcvContextShareErr_RMASK 0x1
#define QIB_7322_ErrStatus_SendVLMismatchErr_LSB 0x24
#define QIB_7322_ErrStatus_SendVLMismatchErr_MSB 0x24
#define QIB_7322_ErrStatus_SendVLMismatchErr_RMASK 0x1
#define QIB_7322_ErrStatus_SendArmLaunchErr_LSB 0x23
#define QIB_7322_ErrStatus_SendArmLaunchErr_MSB 0x23
#define QIB_7322_ErrStatus_SendArmLaunchErr_RMASK 0x1
#define QIB_7322_ErrStatus_SendSpecialTriggerErr_LSB 0x1B
#define QIB_7322_ErrStatus_SendSpecialTriggerErr_MSB 0x1B
#define QIB_7322_ErrStatus_SendSpecialTriggerErr_RMASK 0x1
#define QIB_7322_ErrStatus_SDmaWrongPortErr_LSB 0x1A
#define QIB_7322_ErrStatus_SDmaWrongPortErr_MSB 0x1A
#define QIB_7322_ErrStatus_SDmaWrongPortErr_RMASK 0x1
#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_LSB 0x19
#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_MSB 0x19
#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_RMASK 0x1
#define QIB_7322_ErrStatus_RcvHdrFullErr_LSB 0xD
#define QIB_7322_ErrStatus_RcvHdrFullErr_MSB 0xD
#define QIB_7322_ErrStatus_RcvHdrFullErr_RMASK 0x1
#define QIB_7322_ErrStatus_RcvEgrFullErr_LSB 0xC
#define QIB_7322_ErrStatus_RcvEgrFullErr_MSB 0xC
#define QIB_7322_ErrStatus_RcvEgrFullErr_RMASK 0x1

#define QIB_7322_ErrClear_OFFS 0x90
#define QIB_7322_ErrClear_DEF 0x0000000000000000
#define QIB_7322_ErrClear_ResetNegatedClear_LSB 0x3F
#define QIB_7322_ErrClear_ResetNegatedClear_MSB 0x3F
#define QIB_7322_ErrClear_ResetNegatedClear_RMASK 0x1
#define QIB_7322_ErrClear_HardwareErrClear_LSB 0x3E
#define QIB_7322_ErrClear_HardwareErrClear_MSB 0x3E
#define QIB_7322_ErrClear_HardwareErrClear_RMASK 0x1
#define QIB_7322_ErrClear_InvalidAddrErrClear_LSB 0x3D
#define QIB_7322_ErrClear_InvalidAddrErrClear_MSB 0x3D
#define QIB_7322_ErrClear_InvalidAddrErrClear_RMASK 0x1
#define QIB_7322_ErrClear_SDmaVL15ErrClear_LSB 0x38
#define QIB_7322_ErrClear_SDmaVL15ErrClear_MSB 0x38
#define QIB_7322_ErrClear_SDmaVL15ErrClear_RMASK 0x1
#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_LSB 0x37
#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_MSB 0x37
#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_LSB 0x35
#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_MSB 0x35
#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1
#define QIB_7322_ErrClear_RcvContextShareErrClear_LSB 0x34
#define QIB_7322_ErrClear_RcvContextShareErrClear_MSB 0x34
#define QIB_7322_ErrClear_RcvContextShareErrClear_RMASK 0x1
#define QIB_7322_ErrClear_SendVLMismatchErrMask_LSB 0x24
#define QIB_7322_ErrClear_SendVLMismatchErrMask_MSB 0x24
#define QIB_7322_ErrClear_SendVLMismatchErrMask_RMASK 0x1
#define QIB_7322_ErrClear_SendArmLaunchErrClear_LSB 0x23
#define QIB_7322_ErrClear_SendArmLaunchErrClear_MSB 0x23
#define QIB_7322_ErrClear_SendArmLaunchErrClear_RMASK 0x1
#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_LSB 0x1B
#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_MSB 0x1B
#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1
#define QIB_7322_ErrClear_SDmaWrongPortErrClear_LSB 0x1A
#define QIB_7322_ErrClear_SDmaWrongPortErrClear_MSB 0x1A
#define QIB_7322_ErrClear_SDmaWrongPortErrClear_RMASK 0x1
#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_LSB 0x19
#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_MSB 0x19
#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_RMASK 0x1
#define QIB_7322_ErrClear_RcvHdrFullErrClear_LSB 0xD
#define QIB_7322_ErrClear_RcvHdrFullErrClear_MSB 0xD
#define QIB_7322_ErrClear_RcvHdrFullErrClear_RMASK 0x1
#define QIB_7322_ErrClear_RcvEgrFullErrClear_LSB 0xC
#define QIB_7322_ErrClear_RcvEgrFullErrClear_MSB 0xC
#define QIB_7322_ErrClear_RcvEgrFullErrClear_RMASK 0x1

#define QIB_7322_HwErrMask_OFFS 0x98
#define QIB_7322_HwErrMask_DEF 0x0000000000000000
#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_LSB 0x3F
#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_MSB 0x3F
#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_RMASK 0x1
#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_LSB 0x3E
#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_MSB 0x3E
#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_RMASK 0x1
#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_LSB 0x37
#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_MSB 0x37
#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_RMASK 0x1
#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_LSB 0x36
#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_MSB 0x36
#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1
#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_LSB 0x35
#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_MSB 0x35
#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_RMASK 0x1
#define QIB_7322_HwErrMask_MemoryErrMask_LSB 0x30
#define QIB_7322_HwErrMask_MemoryErrMask_MSB 0x30
#define QIB_7322_HwErrMask_MemoryErrMask_RMASK 0x1
#define QIB_7322_HwErrMask_pcie_phy_txParityErr_LSB 0x22
#define QIB_7322_HwErrMask_pcie_phy_txParityErr_MSB 0x22
#define QIB_7322_HwErrMask_pcie_phy_txParityErr_RMASK 0x1
#define QIB_7322_HwErrMask_PCIeBusParityErrMask_LSB 0x1F
#define QIB_7322_HwErrMask_PCIeBusParityErrMask_MSB 0x21
#define QIB_7322_HwErrMask_PCIeBusParityErrMask_RMASK 0x7
#define QIB_7322_HwErrMask_PcieCplTimeoutMask_LSB 0x1E
#define QIB_7322_HwErrMask_PcieCplTimeoutMask_MSB 0x1E
#define QIB_7322_HwErrMask_PcieCplTimeoutMask_RMASK 0x1
#define QIB_7322_HwErrMask_PciePoisonedTLPMask_LSB 0x1D
#define QIB_7322_HwErrMask_PciePoisonedTLPMask_MSB 0x1D
#define QIB_7322_HwErrMask_PciePoisonedTLPMask_RMASK 0x1
#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_LSB 0x1C
#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_MSB 0x1C
#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_RMASK 0x1
#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_LSB 0x1B
#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_MSB 0x1B
#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_RMASK 0x1
#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_LSB 0xF
#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_MSB 0xF
#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_RMASK 0x1
#define QIB_7322_HwErrMask_statusValidNoEopMask_1_LSB 0xE
#define QIB_7322_HwErrMask_statusValidNoEopMask_1_MSB 0xE
#define QIB_7322_HwErrMask_statusValidNoEopMask_1_RMASK 0x1
#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_LSB 0xD
#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_MSB 0xD
#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_RMASK 0x1
#define QIB_7322_HwErrMask_statusValidNoEopMask_0_LSB 0xC
#define QIB_7322_HwErrMask_statusValidNoEopMask_0_MSB 0xC
#define QIB_7322_HwErrMask_statusValidNoEopMask_0_RMASK 0x1
#define QIB_7322_HwErrMask_LATriggeredMask_LSB 0xB
#define QIB_7322_HwErrMask_LATriggeredMask_MSB 0xB
#define QIB_7322_HwErrMask_LATriggeredMask_RMASK 0x1

#define QIB_7322_HwErrStatus_OFFS 0xA0
#define QIB_7322_HwErrStatus_DEF 0x0000000000000000
#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_LSB 0x3F
#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_MSB 0x3F
#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_RMASK 0x1
#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_LSB 0x3E
#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_MSB 0x3E
#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_RMASK 0x1
#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_LSB 0x37
#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_MSB 0x37
#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_RMASK 0x1
#define QIB_7322_HwErrStatus_PowerOnBISTFailed_LSB 0x36
#define QIB_7322_HwErrStatus_PowerOnBISTFailed_MSB 0x36
#define QIB_7322_HwErrStatus_PowerOnBISTFailed_RMASK 0x1
#define QIB_7322_HwErrStatus_TempsenseTholdReached_LSB 0x35
#define QIB_7322_HwErrStatus_TempsenseTholdReached_MSB 0x35
#define QIB_7322_HwErrStatus_TempsenseTholdReached_RMASK 0x1
#define QIB_7322_HwErrStatus_MemoryErr_LSB 0x30
#define QIB_7322_HwErrStatus_MemoryErr_MSB 0x30
#define QIB_7322_HwErrStatus_MemoryErr_RMASK 0x1
#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_LSB 0x22
#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_MSB 0x22
#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_RMASK 0x1
#define QIB_7322_HwErrStatus_PCIeBusParity_LSB 0x1F
#define QIB_7322_HwErrStatus_PCIeBusParity_MSB 0x21
#define QIB_7322_HwErrStatus_PCIeBusParity_RMASK 0x7
#define QIB_7322_HwErrStatus_PcieCplTimeout_LSB 0x1E
#define QIB_7322_HwErrStatus_PcieCplTimeout_MSB 0x1E
#define QIB_7322_HwErrStatus_PcieCplTimeout_RMASK 0x1
#define QIB_7322_HwErrStatus_PciePoisonedTLP_LSB 0x1D
#define QIB_7322_HwErrStatus_PciePoisonedTLP_MSB 0x1D
#define QIB_7322_HwErrStatus_PciePoisonedTLP_RMASK 0x1
#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_LSB 0x1C
#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_MSB 0x1C
#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_RMASK 0x1
#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_LSB 0x1B
#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_MSB 0x1B
#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_RMASK 0x1
#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_LSB 0xF
#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_MSB 0xF
#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_RMASK 0x1
#define QIB_7322_HwErrStatus_statusValidNoEop_1_LSB 0xE
#define QIB_7322_HwErrStatus_statusValidNoEop_1_MSB 0xE
#define QIB_7322_HwErrStatus_statusValidNoEop_1_RMASK 0x1
#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_LSB 0xD
#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_MSB 0xD
#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_RMASK 0x1
#define QIB_7322_HwErrStatus_statusValidNoEop_0_LSB 0xC
#define QIB_7322_HwErrStatus_statusValidNoEop_0_MSB 0xC
#define QIB_7322_HwErrStatus_statusValidNoEop_0_RMASK 0x1
#define QIB_7322_HwErrStatus_LATriggered_LSB 0xB
#define QIB_7322_HwErrStatus_LATriggered_MSB 0xB
#define QIB_7322_HwErrStatus_LATriggered_RMASK 0x1

#define QIB_7322_HwErrClear_OFFS 0xA8
#define QIB_7322_HwErrClear_DEF 0x0000000000000000
#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_LSB 0x3F
#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_MSB 0x3F
#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_RMASK 0x1
#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_LSB 0x3E
#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_MSB 0x3E
#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_RMASK 0x1
#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_LSB 0x37
#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_MSB 0x37
#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_RMASK 0x1
#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_LSB 0x36
#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_MSB 0x36
#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1
#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_LSB 0x35
#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_MSB 0x35
#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_RMASK 0x1
#define QIB_7322_HwErrClear_MemoryErrClear_LSB 0x30
#define QIB_7322_HwErrClear_MemoryErrClear_MSB 0x30
#define QIB_7322_HwErrClear_MemoryErrClear_RMASK 0x1
#define QIB_7322_HwErrClear_pcie_phy_txParityErr_LSB 0x22
#define QIB_7322_HwErrClear_pcie_phy_txParityErr_MSB 0x22
#define QIB_7322_HwErrClear_pcie_phy_txParityErr_RMASK 0x1
#define QIB_7322_HwErrClear_PCIeBusParityClear_LSB 0x1F
#define QIB_7322_HwErrClear_PCIeBusParityClear_MSB 0x21
#define QIB_7322_HwErrClear_PCIeBusParityClear_RMASK 0x7
#define QIB_7322_HwErrClear_PcieCplTimeoutClear_LSB 0x1E
#define QIB_7322_HwErrClear_PcieCplTimeoutClear_MSB 0x1E
#define QIB_7322_HwErrClear_PcieCplTimeoutClear_RMASK 0x1
#define QIB_7322_HwErrClear_PciePoisonedTLPClear_LSB 0x1D
#define QIB_7322_HwErrClear_PciePoisonedTLPClear_MSB 0x1D
#define QIB_7322_HwErrClear_PciePoisonedTLPClear_RMASK 0x1
#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_LSB 0x1C
#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_MSB 0x1C
#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_RMASK 0x1
#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_LSB 0x1B
#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_MSB 0x1B
#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_RMASK 0x1
#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_LSB 0xF
#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_MSB 0xF
#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_RMASK 0x1
#define QIB_7322_HwErrClear_IBCBusToSPCparityErrClear_1_LSB 0xE
#define QIB_7322_HwErrClear_IBCBusToSPCparityErrClear_1_MSB 0xE
#define QIB_7322_HwErrClear_IBCBusToSPCparityErrClear_1_RMASK 0x1
#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_LSB 0xD
#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_MSB 0xD
#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_RMASK 0x1
#define QIB_7322_HwErrClear_IBCBusToSPCparityErrClear_0_LSB 0xC
#define QIB_7322_HwErrClear_IBCBusToSPCparityErrClear_0_MSB 0xC
#define QIB_7322_HwErrClear_IBCBusToSPCparityErrClear_0_RMASK 0x1
#define QIB_7322_HwErrClear_LATriggeredClear_LSB 0xB
#define QIB_7322_HwErrClear_LATriggeredClear_MSB 0xB
#define QIB_7322_HwErrClear_LATriggeredClear_RMASK 0x1

#define QIB_7322_HwDiagCtrl_OFFS 0xB0
#define QIB_7322_HwDiagCtrl_DEF 0x0000000000000000
#define QIB_7322_HwDiagCtrl_Diagnostic_LSB 0x3F
#define QIB_7322_HwDiagCtrl_Diagnostic_MSB 0x3F
#define QIB_7322_HwDiagCtrl_Diagnostic_RMASK 0x1
#define QIB_7322_HwDiagCtrl_CounterWrEnable_LSB 0x3D
#define QIB_7322_HwDiagCtrl_CounterWrEnable_MSB 0x3D
#define QIB_7322_HwDiagCtrl_CounterWrEnable_RMASK 0x1
#define QIB_7322_HwDiagCtrl_CounterDisable_LSB 0x3C
#define QIB_7322_HwDiagCtrl_CounterDisable_MSB 0x3C
#define QIB_7322_HwDiagCtrl_CounterDisable_RMASK 0x1
#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F
#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_MSB 0x22
#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF
#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_LSB 0xF
#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_MSB 0xF
#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_RMASK 0x1
#define QIB_7322_HwDiagCtrl_ForcestatusValidNoEop_1_LSB 0xE
#define QIB_7322_HwDiagCtrl_ForcestatusValidNoEop_1_MSB 0xE
#define QIB_7322_HwDiagCtrl_ForcestatusValidNoEop_1_RMASK 0x1
#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_LSB 0xD
#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_MSB 0xD
#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_RMASK 0x1
#define QIB_7322_HwDiagCtrl_ForcestatusValidNoEop_0_LSB 0xC
#define QIB_7322_HwDiagCtrl_ForcestatusValidNoEop_0_MSB 0xC
#define QIB_7322_HwDiagCtrl_ForcestatusValidNoEop_0_RMASK 0x1

#define QIB_7322_EXTStatus_OFFS 0xC0
#define QIB_7322_EXTStatus_DEF 0x000000000000X000
#define QIB_7322_EXTStatus_GPIOIn_LSB 0x30
#define QIB_7322_EXTStatus_GPIOIn_MSB 0x3F
#define QIB_7322_EXTStatus_GPIOIn_RMASK 0xFFFF
#define QIB_7322_EXTStatus_MemBISTDisabled_LSB 0xF
#define QIB_7322_EXTStatus_MemBISTDisabled_MSB 0xF
#define QIB_7322_EXTStatus_MemBISTDisabled_RMASK 0x1
#define QIB_7322_EXTStatus_MemBISTEndTest_LSB 0xE
#define QIB_7322_EXTStatus_MemBISTEndTest_MSB 0xE
#define QIB_7322_EXTStatus_MemBISTEndTest_RMASK 0x1

#define QIB_7322_EXTCtrl_OFFS 0xC8
#define QIB_7322_EXTCtrl_DEF 0x0000000000000000
#define QIB_7322_EXTCtrl_GPIOOe_LSB 0x30
#define QIB_7322_EXTCtrl_GPIOOe_MSB 0x3F
#define QIB_7322_EXTCtrl_GPIOOe_RMASK 0xFFFF
#define QIB_7322_EXTCtrl_GPIOInvert_LSB 0x20
#define QIB_7322_EXTCtrl_GPIOInvert_MSB 0x2F
#define QIB_7322_EXTCtrl_GPIOInvert_RMASK 0xFFFF
#define QIB_7322_EXTCtrl_LEDPort1GreenOn_LSB 0x3
#define QIB_7322_EXTCtrl_LEDPort1GreenOn_MSB 0x3
#define QIB_7322_EXTCtrl_LEDPort1GreenOn_RMASK 0x1
#define QIB_7322_EXTCtrl_LEDPort1YellowOn_LSB 0x2
#define QIB_7322_EXTCtrl_LEDPort1YellowOn_MSB 0x2
#define QIB_7322_EXTCtrl_LEDPort1YellowOn_RMASK 0x1
#define QIB_7322_EXTCtrl_LEDPort0GreenOn_LSB 0x1
#define QIB_7322_EXTCtrl_LEDPort0GreenOn_MSB 0x1
#define QIB_7322_EXTCtrl_LEDPort0GreenOn_RMASK 0x1
#define QIB_7322_EXTCtrl_LEDPort0YellowOn_LSB 0x0
#define QIB_7322_EXTCtrl_LEDPort0YellowOn_MSB 0x0
#define QIB_7322_EXTCtrl_LEDPort0YellowOn_RMASK 0x1

#define QIB_7322_GPIODebugSelReg_OFFS 0xD8
#define QIB_7322_GPIODebugSelReg_DEF 0x0000000000000000
#define QIB_7322_GPIODebugSelReg_SelPulse_LSB 0x10
#define QIB_7322_GPIODebugSelReg_SelPulse_MSB 0x1F
#define QIB_7322_GPIODebugSelReg_SelPulse_RMASK 0xFFFF
#define QIB_7322_GPIODebugSelReg_GPIOSourceSelDebug_LSB 0x0
#define QIB_7322_GPIODebugSelReg_GPIOSourceSelDebug_MSB 0xF
#define QIB_7322_GPIODebugSelReg_GPIOSourceSelDebug_RMASK 0xFFFF

#define QIB_7322_GPIOOut_OFFS 0xE0
#define QIB_7322_GPIOOut_DEF 0x0000000000000000

#define QIB_7322_GPIOMask_OFFS 0xE8
#define QIB_7322_GPIOMask_DEF 0x0000000000000000

#define QIB_7322_GPIOStatus_OFFS 0xF0
#define QIB_7322_GPIOStatus_DEF 0x0000000000000000

#define QIB_7322_GPIOClear_OFFS 0xF8
#define QIB_7322_GPIOClear_DEF 0x0000000000000000

#define QIB_7322_RcvCtrl_OFFS 0x100
#define QIB_7322_RcvCtrl_DEF 0x0000000000000000
#define QIB_7322_RcvCtrl_TidReDirect_LSB 0x30
#define QIB_7322_RcvCtrl_TidReDirect_MSB 0x3F
#define QIB_7322_RcvCtrl_TidReDirect_RMASK 0xFFFF
#define QIB_7322_RcvCtrl_TailUpd_LSB 0x2F
#define QIB_7322_RcvCtrl_TailUpd_MSB 0x2F
#define QIB_7322_RcvCtrl_TailUpd_RMASK 0x1
#define QIB_7322_RcvCtrl_XrcTypeCode_LSB 0x2C
#define QIB_7322_RcvCtrl_XrcTypeCode_MSB 0x2E
#define QIB_7322_RcvCtrl_XrcTypeCode_RMASK 0x7
#define QIB_7322_RcvCtrl_TidFlowEnable_LSB 0x2B
#define QIB_7322_RcvCtrl_TidFlowEnable_MSB 0x2B
#define QIB_7322_RcvCtrl_TidFlowEnable_RMASK 0x1
#define QIB_7322_RcvCtrl_ContextCfg_LSB 0x29
#define QIB_7322_RcvCtrl_ContextCfg_MSB 0x2A
#define QIB_7322_RcvCtrl_ContextCfg_RMASK 0x3
#define QIB_7322_RcvCtrl_IntrAvail_LSB 0x14
#define QIB_7322_RcvCtrl_IntrAvail_MSB 0x25
#define QIB_7322_RcvCtrl_IntrAvail_RMASK 0x3FFFF
#define QIB_7322_RcvCtrl_dontDropRHQFull_LSB 0x0
#define QIB_7322_RcvCtrl_dontDropRHQFull_MSB 0x11
#define QIB_7322_RcvCtrl_dontDropRHQFull_RMASK 0x3FFFF

#define QIB_7322_RcvHdrSize_OFFS 0x110
#define QIB_7322_RcvHdrSize_DEF 0x0000000000000000

#define QIB_7322_RcvHdrCnt_OFFS 0x118
#define QIB_7322_RcvHdrCnt_DEF 0x0000000000000000

#define QIB_7322_RcvHdrEntSize_OFFS 0x120
#define QIB_7322_RcvHdrEntSize_DEF 0x0000000000000000

#define QIB_7322_RcvTIDBase_OFFS 0x128
#define QIB_7322_RcvTIDBase_DEF 0x0000000000050000

#define QIB_7322_RcvTIDCnt_OFFS 0x130
#define QIB_7322_RcvTIDCnt_DEF 0x0000000000000200

#define QIB_7322_RcvEgrBase_OFFS 0x138
#define QIB_7322_RcvEgrBase_DEF 0x0000000000014000

#define QIB_7322_RcvEgrCnt_OFFS 0x140
#define QIB_7322_RcvEgrCnt_DEF 0x0000000000001000

#define QIB_7322_RcvBufBase_OFFS 0x148
#define QIB_7322_RcvBufBase_DEF 0x0000000000080000

#define QIB_7322_RcvBufSize_OFFS 0x150
#define QIB_7322_RcvBufSize_DEF 0x0000000000005000

#define QIB_7322_RxIntMemBase_OFFS 0x158
#define QIB_7322_RxIntMemBase_DEF 0x0000000000077000

#define QIB_7322_RxIntMemSize_OFFS 0x160
#define QIB_7322_RxIntMemSize_DEF 0x0000000000007000

#define QIB_7322_encryption_key_low_OFFS 0x180
#define QIB_7322_encryption_key_low_DEF 0x0000000000000000

#define QIB_7322_encryption_key_high_OFFS 0x188
#define QIB_7322_encryption_key_high_DEF 0x0000000000000000

#define QIB_7322_feature_mask_OFFS 0x190
#define QIB_7322_feature_mask_DEF 0x00000000000000XX

#define QIB_7322_active_feature_mask_OFFS 0x198
#define QIB_7322_active_feature_mask_DEF 0x00000000000000XX
#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_LSB 0x5
#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_MSB 0x5
#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_RMASK 0x1
#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_LSB 0x4
#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_MSB 0x4
#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_RMASK 0x1
#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_LSB 0x3
#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_MSB 0x3
#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_RMASK 0x1
#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_LSB 0x2
#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_MSB 0x2
#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_RMASK 0x1
#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_LSB 0x1
#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_MSB 0x1
#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_RMASK 0x1
#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_LSB 0x0
#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_MSB 0x0
#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_RMASK 0x1

#define QIB_7322_SendCtrl_OFFS 0x1C0
#define QIB_7322_SendCtrl_DEF 0x0000000000000000
#define QIB_7322_SendCtrl_Disarm_LSB 0x1F
#define QIB_7322_SendCtrl_Disarm_MSB 0x1F
#define QIB_7322_SendCtrl_Disarm_RMASK 0x1
#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_LSB 0x1D
#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_MSB 0x1D
#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_RMASK 0x1
#define QIB_7322_SendCtrl_AvailUpdThld_LSB 0x18
#define QIB_7322_SendCtrl_AvailUpdThld_MSB 0x1C
#define QIB_7322_SendCtrl_AvailUpdThld_RMASK 0x1F
#define QIB_7322_SendCtrl_DisarmSendBuf_LSB 0x10
#define QIB_7322_SendCtrl_DisarmSendBuf_MSB 0x17
#define QIB_7322_SendCtrl_DisarmSendBuf_RMASK 0xFF
#define QIB_7322_SendCtrl_SpecialTriggerEn_LSB 0x4
#define QIB_7322_SendCtrl_SpecialTriggerEn_MSB 0x4
#define QIB_7322_SendCtrl_SpecialTriggerEn_RMASK 0x1
#define QIB_7322_SendCtrl_SendBufAvailUpd_LSB 0x2
#define QIB_7322_SendCtrl_SendBufAvailUpd_MSB 0x2
#define QIB_7322_SendCtrl_SendBufAvailUpd_RMASK 0x1
#define QIB_7322_SendCtrl_SendIntBufAvail_LSB 0x1
#define QIB_7322_SendCtrl_SendIntBufAvail_MSB 0x1
#define QIB_7322_SendCtrl_SendIntBufAvail_RMASK 0x1

#define QIB_7322_SendBufBase_OFFS 0x1C8
#define QIB_7322_SendBufBase_DEF 0x0018000000100000
#define QIB_7322_SendBufBase_BaseAddr_LargePIO_LSB 0x20
#define QIB_7322_SendBufBase_BaseAddr_LargePIO_MSB 0x34
#define QIB_7322_SendBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF
#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_LSB 0x0
#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_MSB 0x14
#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF

#define QIB_7322_SendBufSize_OFFS 0x1D0
#define QIB_7322_SendBufSize_DEF 0x0000108000000880
#define QIB_7322_SendBufSize_Size_LargePIO_LSB 0x20
#define QIB_7322_SendBufSize_Size_LargePIO_MSB 0x2C
#define QIB_7322_SendBufSize_Size_LargePIO_RMASK 0x1FFF
#define QIB_7322_SendBufSize_Size_SmallPIO_LSB 0x0
#define QIB_7322_SendBufSize_Size_SmallPIO_MSB 0xB
#define QIB_7322_SendBufSize_Size_SmallPIO_RMASK 0xFFF

#define QIB_7322_SendBufCnt_OFFS 0x1D8
#define QIB_7322_SendBufCnt_DEF 0x0000002000000080
#define QIB_7322_SendBufCnt_Num_LargeBuffers_LSB 0x20
#define QIB_7322_SendBufCnt_Num_LargeBuffers_MSB 0x25
#define QIB_7322_SendBufCnt_Num_LargeBuffers_RMASK 0x3F
#define QIB_7322_SendBufCnt_Num_SmallBuffers_LSB 0x0
#define QIB_7322_SendBufCnt_Num_SmallBuffers_MSB 0x8
#define QIB_7322_SendBufCnt_Num_SmallBuffers_RMASK 0x1FF

#define QIB_7322_SendBufAvailAddr_OFFS 0x1E0
#define QIB_7322_SendBufAvailAddr_DEF 0x0000000000000000
#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_LSB 0x6
#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_MSB 0x27
#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_RMASK 0x3FFFFFFFF

#define QIB_7322_TxIntMemBase_OFFS 0x1E8
#define QIB_7322_TxIntMemBase_DEF 0x0000000000064000

#define QIB_7322_TxIntMemSize_OFFS 0x1F0
#define QIB_7322_TxIntMemSize_DEF 0x000000000000C000

#define QIB_7322_SendBufErr0_OFFS 0x240
#define QIB_7322_SendBufErr0_DEF 0x0000000000000000
#define QIB_7322_SendBufErr0_SendBufErr_63_0_LSB 0x0
#define QIB_7322_SendBufErr0_SendBufErr_63_0_MSB 0x3F
#define QIB_7322_SendBufErr0_SendBufErr_63_0_RMASK 0x0

#define QIB_7322_AvailUpdCount_OFFS 0x268
#define QIB_7322_AvailUpdCount_DEF 0x0000000000000000
#define QIB_7322_AvailUpdCount_AvailUpdCount_LSB 0x0
#define QIB_7322_AvailUpdCount_AvailUpdCount_MSB 0x4
#define QIB_7322_AvailUpdCount_AvailUpdCount_RMASK 0x1F

#define QIB_7322_RcvHdrAddr0_OFFS 0x280
#define QIB_7322_RcvHdrAddr0_DEF 0x0000000000000000
#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_LSB 0x2
#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_MSB 0x27
#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_RMASK 0x3FFFFFFFFF

#define QIB_7322_RcvHdrTailAddr0_OFFS 0x340
#define QIB_7322_RcvHdrTailAddr0_DEF 0x0000000000000000
#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_LSB 0x2
#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_MSB 0x27
#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_RMASK 0x3FFFFFFFFF

#define QIB_7322_EEPCtlStat_OFFS 0x3E8
#define QIB_7322_EEPCtlStat_DEF 0x0000000000000002
#define QIB_7322_EEPCtlStat_CtlrStat_LSB 0x1F
#define QIB_7322_EEPCtlStat_CtlrStat_MSB 0x1F
#define QIB_7322_EEPCtlStat_CtlrStat_RMASK 0x1
#define QIB_7322_EEPCtlStat_CmdWrErr_LSB 0x6
#define QIB_7322_EEPCtlStat_CmdWrErr_MSB 0x6
#define QIB_7322_EEPCtlStat_CmdWrErr_RMASK 0x1
#define QIB_7322_EEPCtlStat_LstDatWr_LSB 0x5
#define QIB_7322_EEPCtlStat_LstDatWr_MSB 0x5
#define QIB_7322_EEPCtlStat_LstDatWr_RMASK 0x1
#define QIB_7322_EEPCtlStat_PageMode_LSB 0x4
#define QIB_7322_EEPCtlStat_PageMode_MSB 0x4
#define QIB_7322_EEPCtlStat_PageMode_RMASK 0x1
#define QIB_7322_EEPCtlStat_ByteProg_LSB 0x3
#define QIB_7322_EEPCtlStat_ByteProg_MSB 0x3
#define QIB_7322_EEPCtlStat_ByteProg_RMASK 0x1
#define QIB_7322_EEPCtlStat_EPReset_LSB 0x2
#define QIB_7322_EEPCtlStat_EPReset_MSB 0x2
#define QIB_7322_EEPCtlStat_EPReset_RMASK 0x1
#define QIB_7322_EEPCtlStat_EPAccEn_LSB 0x0
#define QIB_7322_EEPCtlStat_EPAccEn_MSB 0x1
#define QIB_7322_EEPCtlStat_EPAccEn_RMASK 0x3

#define QIB_7322_EEPAddrCmd_OFFS 0x3F0
#define QIB_7322_EEPAddrCmd_DEF 0x0000000000000000
#define QIB_7322_EEPAddrCmd_EPCmd_LSB 0x18
#define QIB_7322_EEPAddrCmd_EPCmd_MSB 0x1F
#define QIB_7322_EEPAddrCmd_EPCmd_RMASK 0xFF
#define QIB_7322_EEPAddrCmd_EPAddr_LSB 0x0
#define QIB_7322_EEPAddrCmd_EPAddr_MSB 0x17
#define QIB_7322_EEPAddrCmd_EPAddr_RMASK 0xFFFFFF

#define QIB_7322_EEPData_OFFS 0x3F8
#define QIB_7322_EEPData_DEF 0x0000000000000000

#define QIB_7322_efuse_control_reg_OFFS 0x410
#define QIB_7322_efuse_control_reg_DEF 0x0000000080000000
#define QIB_7322_efuse_control_reg_rdy_LSB 0x1F
#define QIB_7322_efuse_control_reg_rdy_MSB 0x1F
#define QIB_7322_efuse_control_reg_rdy_RMASK 0x1
#define QIB_7322_efuse_control_reg_read_data_valid_LSB 0x1E
#define QIB_7322_efuse_control_reg_read_data_valid_MSB 0x1E
#define QIB_7322_efuse_control_reg_read_data_valid_RMASK 0x1
#define QIB_7322_efuse_control_reg_req_err_LSB 0x1D
#define QIB_7322_efuse_control_reg_req_err_MSB 0x1D
#define QIB_7322_efuse_control_reg_req_err_RMASK 0x1
#define QIB_7322_efuse_control_reg_start_operation_LSB 0x18
#define QIB_7322_efuse_control_reg_start_operation_MSB 0x18
#define QIB_7322_efuse_control_reg_start_operation_RMASK 0x1
#define QIB_7322_efuse_control_reg_operation_LSB 0x16
#define QIB_7322_efuse_control_reg_operation_MSB 0x17
#define QIB_7322_efuse_control_reg_operation_RMASK 0x3
#define QIB_7322_efuse_control_reg_last_program_address_LSB 0xB
#define QIB_7322_efuse_control_reg_last_program_address_MSB 0x15
#define QIB_7322_efuse_control_reg_last_program_address_RMASK 0x7FF
#define QIB_7322_efuse_control_reg_address_LSB 0x0
#define QIB_7322_efuse_control_reg_address_MSB 0xA
#define QIB_7322_efuse_control_reg_address_RMASK 0x7FF

#define QIB_7322_efuse_data_reg_OFFS 0x418
#define QIB_7322_efuse_data_reg_DEF 0x0000000000000000

#define QIB_7322_voltage_margin_reg_OFFS 0x428
#define QIB_7322_voltage_margin_reg_DEF 0x0000000000000000
#define QIB_7322_voltage_margin_reg_voltage_margin_settings_LSB 0x1
#define QIB_7322_voltage_margin_reg_voltage_margin_settings_MSB 0x2
#define QIB_7322_voltage_margin_reg_voltage_margin_settings_RMASK 0x3
#define QIB_7322_voltage_margin_reg_voltage_margin_settings_enable_LSB 0x0
#define QIB_7322_voltage_margin_reg_voltage_margin_settings_enable_MSB 0x0
#define QIB_7322_voltage_margin_reg_voltage_margin_settings_enable_RMASK 0x1

#define QIB_7322_VTSense_reg_OFFS 0x430
#define QIB_7322_VTSense_reg_DEF 0x0000000000000020
#define QIB_7322_VTSense_reg_output_valid_LSB 0x1F
#define QIB_7322_VTSense_reg_output_valid_MSB 0x1F
#define QIB_7322_VTSense_reg_output_valid_RMASK 0x1
#define QIB_7322_VTSense_reg_threshold_limbit_LSB 0x1B
#define QIB_7322_VTSense_reg_threshold_limbit_MSB 0x1B
#define QIB_7322_VTSense_reg_threshold_limbit_RMASK 0x1
#define QIB_7322_VTSense_reg_sensor_output_data_LSB 0x10
#define QIB_7322_VTSense_reg_sensor_output_data_MSB 0x19
#define QIB_7322_VTSense_reg_sensor_output_data_RMASK 0x3FF
#define QIB_7322_VTSense_reg_threshold_LSB 0x6
#define QIB_7322_VTSense_reg_threshold_MSB 0xF
#define QIB_7322_VTSense_reg_threshold_RMASK 0x3FF
#define QIB_7322_VTSense_reg_power_down_LSB 0x5
#define QIB_7322_VTSense_reg_power_down_MSB 0x5
#define QIB_7322_VTSense_reg_power_down_RMASK 0x1
#define QIB_7322_VTSense_reg_start_busy_LSB 0x4
#define QIB_7322_VTSense_reg_start_busy_MSB 0x4
#define QIB_7322_VTSense_reg_start_busy_RMASK 0x1
#define QIB_7322_VTSense_reg_adc_mode_LSB 0x3
#define QIB_7322_VTSense_reg_adc_mode_MSB 0x3
#define QIB_7322_VTSense_reg_adc_mode_RMASK 0x1
#define QIB_7322_VTSense_reg_temp_sense_select_LSB 0x0
#define QIB_7322_VTSense_reg_temp_sense_select_MSB 0x2
#define QIB_7322_VTSense_reg_temp_sense_select_RMASK 0x7

#define QIB_7322_procmon_reg_OFFS 0x438
#define QIB_7322_procmon_reg_DEF 0x0000000000000000
#define QIB_7322_procmon_reg_procmon_count_valid_LSB 0x1F
#define QIB_7322_procmon_reg_procmon_count_valid_MSB 0x1F
#define QIB_7322_procmon_reg_procmon_count_valid_RMASK 0x1
#define QIB_7322_procmon_reg_procmon_count_LSB 0x10
#define QIB_7322_procmon_reg_procmon_count_MSB 0x1B
#define QIB_7322_procmon_reg_procmon_count_RMASK 0xFFF
#define QIB_7322_procmon_reg_start_counter_LSB 0xF
#define QIB_7322_procmon_reg_start_counter_MSB 0xF
#define QIB_7322_procmon_reg_start_counter_RMASK 0x1
#define QIB_7322_procmon_reg_ring_osc_select_LSB 0x0
#define QIB_7322_procmon_reg_ring_osc_select_MSB 0x2
#define QIB_7322_procmon_reg_ring_osc_select_RMASK 0x7

#define QIB_7322_PcieRbufTestReg0_OFFS 0x440
#define QIB_7322_PcieRbufTestReg0_DEF 0x0000000000000000

#define QIB_7322_ahb_access_ctrl_OFFS 0x460
#define QIB_7322_ahb_access_ctrl_DEF 0x0000000000000000
#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_LSB 0x1
#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_MSB 0x2
#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_RMASK 0x3
#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_LSB 0x0
#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_MSB 0x0
#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_RMASK 0x1

#define QIB_7322_ahb_transaction_reg_OFFS 0x468
#define QIB_7322_ahb_transaction_reg_DEF 0x0000000080000000
#define QIB_7322_ahb_transaction_reg_ahb_data_LSB 0x20
#define QIB_7322_ahb_transaction_reg_ahb_data_MSB 0x3F
#define QIB_7322_ahb_transaction_reg_ahb_data_RMASK 0xFFFFFFFF
#define QIB_7322_ahb_transaction_reg_ahb_rdy_LSB 0x1F
#define QIB_7322_ahb_transaction_reg_ahb_rdy_MSB 0x1F
#define QIB_7322_ahb_transaction_reg_ahb_rdy_RMASK 0x1
#define QIB_7322_ahb_transaction_reg_ahb_req_err_LSB 0x1E
#define QIB_7322_ahb_transaction_reg_ahb_req_err_MSB 0x1E
#define QIB_7322_ahb_transaction_reg_ahb_req_err_RMASK 0x1
#define QIB_7322_ahb_transaction_reg_write_not_read_LSB 0x1B
#define QIB_7322_ahb_transaction_reg_write_not_read_MSB 0x1B
#define QIB_7322_ahb_transaction_reg_write_not_read_RMASK 0x1
#define QIB_7322_ahb_transaction_reg_ahb_address_LSB 0x10
#define QIB_7322_ahb_transaction_reg_ahb_address_MSB 0x1A
#define QIB_7322_ahb_transaction_reg_ahb_address_RMASK 0x7FF

#define QIB_7322_SPC_JTAG_ACCESS_REG_OFFS 0x470
#define QIB_7322_SPC_JTAG_ACCESS_REG_DEF 0x0000000000000001
#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_LSB 0xA
#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_MSB 0xA
#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_RMASK 0x1
#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_LSB 0x5
#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_MSB 0x9
#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_RMASK 0x1F
#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_LSB 0x3
#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_MSB 0x4
#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_RMASK 0x3
#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_LSB 0x2
#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_MSB 0x2
#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_RMASK 0x1
#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_LSB 0x1
#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_MSB 0x1
#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_RMASK 0x1
#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_LSB 0x0
#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_MSB 0x0
#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_RMASK 0x1

#define QIB_7322_LAControlReg_OFFS 0x478
#define QIB_7322_LAControlReg_DEF 0x0000000100000001
#define QIB_7322_LAControlReg_Delay_sc_LSB 0x2C
#define QIB_7322_LAControlReg_Delay_sc_MSB 0x3F
#define QIB_7322_LAControlReg_Delay_sc_RMASK 0xFFFFF
#define QIB_7322_LAControlReg_Mode_sc_LSB 0x2A
#define QIB_7322_LAControlReg_Mode_sc_MSB 0x2B
#define QIB_7322_LAControlReg_Mode_sc_RMASK 0x3
#define QIB_7322_LAControlReg_Address_sc_LSB 0x21
#define QIB_7322_LAControlReg_Address_sc_MSB 0x29
#define QIB_7322_LAControlReg_Address_sc_RMASK 0x1FF
#define QIB_7322_LAControlReg_Finished_sc_LSB 0x20
#define QIB_7322_LAControlReg_Finished_sc_MSB 0x20
#define QIB_7322_LAControlReg_Finished_sc_RMASK 0x1
#define QIB_7322_LAControlReg_Delay_LSB 0xC
#define QIB_7322_LAControlReg_Delay_MSB 0x1F
#define QIB_7322_LAControlReg_Delay_RMASK 0xFFFFF
#define QIB_7322_LAControlReg_Mode_LSB 0xA
#define QIB_7322_LAControlReg_Mode_MSB 0xB
#define QIB_7322_LAControlReg_Mode_RMASK 0x3
#define QIB_7322_LAControlReg_Address_LSB 0x1
#define QIB_7322_LAControlReg_Address_MSB 0x9
#define QIB_7322_LAControlReg_Address_RMASK 0x1FF
#define QIB_7322_LAControlReg_Finished_LSB 0x0
#define QIB_7322_LAControlReg_Finished_MSB 0x0
#define QIB_7322_LAControlReg_Finished_RMASK 0x1

#define QIB_7322_PcieRhdrTestReg0_OFFS 0x480
#define QIB_7322_PcieRhdrTestReg0_DEF 0x0000000000000000

#define QIB_7322_SendCheckMask0_OFFS 0x4C0
#define QIB_7322_SendCheckMask0_DEF 0x0000000000000000
#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_LSB 0x0
#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_MSB 0x3F
#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_RMASK 0x0

#define QIB_7322_SendGRHCheckMask0_OFFS 0x4E0
#define QIB_7322_SendGRHCheckMask0_DEF 0x0000000000000000
#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_LSB 0x0
#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_MSB 0x3F
#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_RMASK 0x0

#define QIB_7322_SendIBPacketMask0_OFFS 0x500
#define QIB_7322_SendIBPacketMask0_DEF 0x0000000000000000
#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_LSB 0x0
#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_MSB 0x3F
#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_RMASK 0x0

#define QIB_7322_IntRedirect0_OFFS 0x540
#define QIB_7322_IntRedirect0_DEF 0x0000000000000000
#define QIB_7322_IntRedirect0_vec11_LSB 0x37
#define QIB_7322_IntRedirect0_vec11_MSB 0x3B
#define QIB_7322_IntRedirect0_vec11_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec10_LSB 0x32
#define QIB_7322_IntRedirect0_vec10_MSB 0x36
#define QIB_7322_IntRedirect0_vec10_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec9_LSB 0x2D
#define QIB_7322_IntRedirect0_vec9_MSB 0x31
#define QIB_7322_IntRedirect0_vec9_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec8_LSB 0x28
#define QIB_7322_IntRedirect0_vec8_MSB 0x2C
#define QIB_7322_IntRedirect0_vec8_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec7_LSB 0x23
#define QIB_7322_IntRedirect0_vec7_MSB 0x27
#define QIB_7322_IntRedirect0_vec7_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec6_LSB 0x1E
#define QIB_7322_IntRedirect0_vec6_MSB 0x22
#define QIB_7322_IntRedirect0_vec6_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec5_LSB 0x19
#define QIB_7322_IntRedirect0_vec5_MSB 0x1D
#define QIB_7322_IntRedirect0_vec5_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec4_LSB 0x14
#define QIB_7322_IntRedirect0_vec4_MSB 0x18
#define QIB_7322_IntRedirect0_vec4_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec3_LSB 0xF
#define QIB_7322_IntRedirect0_vec3_MSB 0x13
#define QIB_7322_IntRedirect0_vec3_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec2_LSB 0xA
#define QIB_7322_IntRedirect0_vec2_MSB 0xE
#define QIB_7322_IntRedirect0_vec2_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec1_LSB 0x5
#define QIB_7322_IntRedirect0_vec1_MSB 0x9
#define QIB_7322_IntRedirect0_vec1_RMASK 0x1F
#define QIB_7322_IntRedirect0_vec0_LSB 0x0
#define QIB_7322_IntRedirect0_vec0_MSB 0x4
#define QIB_7322_IntRedirect0_vec0_RMASK 0x1F

#define QIB_7322_Int_Granted_OFFS 0x570
#define QIB_7322_Int_Granted_DEF 0x0000000000000000

#define QIB_7322_vec_clr_without_int_OFFS 0x578
#define QIB_7322_vec_clr_without_int_DEF 0x0000000000000000

#define QIB_7322_DCACtrlA_OFFS 0x580
#define QIB_7322_DCACtrlA_DEF 0x0000000000000000
#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_LSB 0x4
#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_MSB 0x4
#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_RMASK 0x1
#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_LSB 0x3
#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_MSB 0x3
#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_RMASK 0x1
#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_LSB 0x2
#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_MSB 0x2
#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_RMASK 0x1
#define QIB_7322_DCACtrlA_EagerDCAEnable_LSB 0x1
#define QIB_7322_DCACtrlA_EagerDCAEnable_MSB 0x1
#define QIB_7322_DCACtrlA_EagerDCAEnable_RMASK 0x1
#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_LSB 0x0
#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_MSB 0x0
#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_RMASK 0x1

#define QIB_7322_DCACtrlB_OFFS 0x588
#define QIB_7322_DCACtrlB_DEF 0x0000000000000000
#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_LSB 0x36
#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_MSB 0x3B
#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_LSB 0x2E
#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_MSB 0x35
#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_LSB 0x28
#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_MSB 0x2D
#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_LSB 0x20
#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_MSB 0x27
#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_LSB 0x16
#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_MSB 0x1B
#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_LSB 0xE
#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_MSB 0x15
#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_LSB 0x8
#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_MSB 0xD
#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_LSB 0x0
#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_MSB 0x7
#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_RMASK 0xFF

#define QIB_7322_DCACtrlC_OFFS 0x590
#define QIB_7322_DCACtrlC_DEF 0x0000000000000000
#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_LSB 0x36
#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_MSB 0x3B
#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_LSB 0x2E
#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_MSB 0x35
#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_LSB 0x28
#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_MSB 0x2D
#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_LSB 0x20
#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_MSB 0x27
#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_LSB 0x16
#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_MSB 0x1B
#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_LSB 0xE
#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_MSB 0x15
#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_LSB 0x8
#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_MSB 0xD
#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_LSB 0x0
#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_MSB 0x7
#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_RMASK 0xFF

#define QIB_7322_DCACtrlD_OFFS 0x598
#define QIB_7322_DCACtrlD_DEF 0x0000000000000000
#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_LSB 0x36
#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_MSB 0x3B
#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_LSB 0x2E
#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_MSB 0x35
#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_LSB 0x28
#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_MSB 0x2D
#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_LSB 0x20
#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_MSB 0x27
#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_LSB 0x16
#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_MSB 0x1B
#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_LSB 0xE
#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_MSB 0x15
#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_LSB 0x8
#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_MSB 0xD
#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_LSB 0x0
#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_MSB 0x7
#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_RMASK 0xFF

#define QIB_7322_DCACtrlE_OFFS 0x5A0
#define QIB_7322_DCACtrlE_DEF 0x0000000000000000
#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_LSB 0x36
#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_MSB 0x3B
#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_LSB 0x2E
#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_MSB 0x35
#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_LSB 0x28
#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_MSB 0x2D
#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_LSB 0x20
#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_MSB 0x27
#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_LSB 0x16
#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_MSB 0x1B
#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_LSB 0xE
#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_MSB 0x15
#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_LSB 0x8
#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_MSB 0xD
#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_LSB 0x0
#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_MSB 0x7
#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_RMASK 0xFF

#define QIB_7322_DCACtrlF_OFFS 0x5A8
#define QIB_7322_DCACtrlF_DEF 0x0000000000000000
#define QIB_7322_DCACtrlF_SendDma1DCAOPH_LSB 0x28
#define QIB_7322_DCACtrlF_SendDma1DCAOPH_MSB 0x2F
#define QIB_7322_DCACtrlF_SendDma1DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlF_SendDma0DCAOPH_LSB 0x20
#define QIB_7322_DCACtrlF_SendDma0DCAOPH_MSB 0x27
#define QIB_7322_DCACtrlF_SendDma0DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_LSB 0x16
#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_MSB 0x1B
#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_LSB 0xE
#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_MSB 0x15
#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_RMASK 0xFF
#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_LSB 0x8
#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_MSB 0xD
#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_RMASK 0x3F
#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_LSB 0x0
#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_MSB 0x7
#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_RMASK 0xFF

#define QIB_7322_MemErrCtrlA_OFFS 0x600
#define QIB_7322_MemErrCtrlA_DEF 0x0000000000000000
#define QIB_7322_MemErrCtrlA_SwapEccDataBits_LSB 0x3F
#define QIB_7322_MemErrCtrlA_SwapEccDataBits_MSB 0x3F
#define QIB_7322_MemErrCtrlA_SwapEccDataBits_RMASK 0x1
#define QIB_7322_MemErrCtrlA_DisableEccCorrection_LSB 0x3E
#define QIB_7322_MemErrCtrlA_DisableEccCorrection_MSB 0x3E
#define QIB_7322_MemErrCtrlA_DisableEccCorrection_RMASK 0x1
#define QIB_7322_MemErrCtrlA_SwapEccDataExtraBits_LSB 0x3D
#define QIB_7322_MemErrCtrlA_SwapEccDataExtraBits_MSB 0x3D
#define QIB_7322_MemErrCtrlA_SwapEccDataExtraBits_RMASK 0x1
#define QIB_7322_MemErrCtrlA_SwapEccDataMsixBits_LSB 0x3C
#define QIB_7322_MemErrCtrlA_SwapEccDataMsixBits_MSB 0x3C
#define QIB_7322_MemErrCtrlA_SwapEccDataMsixBits_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable2_LSB 0x37
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable2_MSB 0x37
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable2_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable1_LSB 0x36
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable1_MSB 0x36
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable0_LSB 0x35
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable0_MSB 0x35
#define QIB_7322_MemErrCtrlA_FSSUncErrMsixTable0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemErrCtrlA_FSSUncErrPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemErrCtrlA_FSSUncErrSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemErrCtrlA_FSSUncErrSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemErrCtrlA_FSSUncErrSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemErrCtrlA_FSSUncErrSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemErrCtrlA_FSSUncErrSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendPbcArray_LSB 0x12
#define QIB_7322_MemErrCtrlA_FSSUncErrSendPbcArray_MSB 0x12
#define QIB_7322_MemErrCtrlA_FSSUncErrSendPbcArray_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufExtra_LSB 0x11
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufExtra_MSB 0x11
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufExtra_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufMain_LSB 0x10
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufMain_MSB 0x10
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufMain_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufVL15_LSB 0xF
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufVL15_MSB 0xF
#define QIB_7322_MemErrCtrlA_FSSUncErrSendBufVL15_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvEgrArray_LSB 0xB
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvEgrArray_MSB 0xB
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvEgrArray_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvTIDArray_LSB 0xA
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvTIDArray_MSB 0xA
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvTIDArray_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemErrCtrlA_FSSUncErrLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemErrCtrlA_FSSUncErrLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvFlags_1_LSB 0x6
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvFlags_1_MSB 0x6
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvFlags_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvBuf_1_LSB 0x5
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvBuf_1_MSB 0x5
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemErrCtrlA_FSSUncErrLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemErrCtrlA_FSSUncErrLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvFlags_0_LSB 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvFlags_0_MSB 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvFlags_0_RMASK 0x1
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvBuf_0_LSB 0x0
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvBuf_0_MSB 0x0
#define QIB_7322_MemErrCtrlA_FSSUncErrRcvBuf_0_RMASK 0x1

#define QIB_7322_MemErrCtrlB_OFFS 0x608
#define QIB_7322_MemErrCtrlB_DEF 0x0000000000000000
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable2_LSB 0x37
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable2_MSB 0x37
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable2_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable1_LSB 0x36
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable1_MSB 0x36
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable0_LSB 0x35
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable0_MSB 0x35
#define QIB_7322_MemErrCtrlB_FSSCorErrMsixTable0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemErrCtrlB_FSSCorErrPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemErrCtrlB_FSSCorErrSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemErrCtrlB_FSSCorErrSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemErrCtrlB_FSSCorErrSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemErrCtrlB_FSSCorErrSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemErrCtrlB_FSSCorErrSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendPbcArray_LSB 0x12
#define QIB_7322_MemErrCtrlB_FSSCorErrSendPbcArray_MSB 0x12
#define QIB_7322_MemErrCtrlB_FSSCorErrSendPbcArray_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufExtra_LSB 0x11
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufExtra_MSB 0x11
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufExtra_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufMain_LSB 0x10
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufMain_MSB 0x10
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufMain_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufVL15_LSB 0xF
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufVL15_MSB 0xF
#define QIB_7322_MemErrCtrlB_FSSCorErrSendBufVL15_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvEgrArray_LSB 0xB
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvEgrArray_MSB 0xB
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvEgrArray_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvTIDArray_LSB 0xA
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvTIDArray_MSB 0xA
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvTIDArray_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemErrCtrlB_FSSCorErrLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemErrCtrlB_FSSCorErrLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvFlags_1_LSB 0x6
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvFlags_1_MSB 0x6
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvFlags_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvBuf_1_LSB 0x5
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvBuf_1_MSB 0x5
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvBuf_1_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemErrCtrlB_FSSCorErrLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemErrCtrlB_FSSCorErrLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvFlags_0_LSB 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvFlags_0_MSB 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvFlags_0_RMASK 0x1
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvBuf_0_LSB 0x0
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvBuf_0_MSB 0x0
#define QIB_7322_MemErrCtrlB_FSSCorErrRcvBuf_0_RMASK 0x1

#define QIB_7322_MemMultiUnCorErrMask_OFFS 0x610
#define QIB_7322_MemMultiUnCorErrMask_DEF 0x0000000000000000
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable2_LSB 0x37
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable2_MSB 0x37
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable2_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable1_LSB 0x36
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable1_MSB 0x36
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable0_LSB 0x35
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable0_MSB 0x35
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskMsixTable0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendPbcArray_LSB 0x12
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendPbcArray_MSB 0x12
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendPbcArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufExtra_LSB 0x11
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufExtra_MSB 0x11
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufExtra_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufMain_LSB 0x10
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufMain_MSB 0x10
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufMain_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufVL15_LSB 0xF
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufVL15_MSB 0xF
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskSendBufVL15_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvEgrArray_LSB 0xB
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvEgrArray_MSB 0xB
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvEgrArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvTIDArray_LSB 0xA
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvTIDArray_MSB 0xA
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvTIDArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvFlags_1_LSB 0x6
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvFlags_1_MSB 0x6
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvFlags_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvBuf_1_LSB 0x5
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvBuf_1_MSB 0x5
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvFlags_0_LSB 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvFlags_0_MSB 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvFlags_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvBuf_0_LSB 0x0
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvBuf_0_MSB 0x0
#define QIB_7322_MemMultiUnCorErrMask_MulUncErrMskRcvBuf_0_RMASK 0x1

#define QIB_7322_MemMultiUnCorErrStatus_OFFS 0x618
#define QIB_7322_MemMultiUnCorErrStatus_DEF 0x0000000000000000
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable2_LSB 0x37
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable2_MSB 0x37
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable2_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable1_LSB 0x36
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable1_MSB 0x36
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable0_LSB 0x35
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable0_MSB 0x35
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusMsixTable0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendPbcArray_LSB 0x12
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendPbcArray_MSB 0x12
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendPbcArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufExtra_LSB 0x11
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufExtra_MSB 0x11
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufExtra_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufMain_LSB 0x10
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufMain_MSB 0x10
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufMain_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufVL15_LSB 0xF
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufVL15_MSB 0xF
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusSendBufVL15_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvEgrArray_LSB 0xB
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvEgrArray_MSB 0xB
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvEgrArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvTIDArray_LSB 0xA
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvTIDArray_MSB 0xA
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvTIDArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvFlags_1_LSB 0x6
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvFlags_1_MSB 0x6
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvFlags_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvBuf_1_LSB 0x5
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvBuf_1_MSB 0x5
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvFlags_0_LSB 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvFlags_0_MSB 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvFlags_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvBuf_0_LSB 0x0
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvBuf_0_MSB 0x0
#define QIB_7322_MemMultiUnCorErrStatus_MulUncErrStatusRcvBuf_0_RMASK 0x1

#define QIB_7322_MemMultiUnCorErrClear_OFFS 0x620
#define QIB_7322_MemMultiUnCorErrClear_DEF 0x0000000000000000
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable2_LSB 0x37
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable2_MSB 0x37
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable2_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable1_LSB 0x36
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable1_MSB 0x36
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable0_LSB 0x35
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable0_MSB 0x35
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearMsixTable0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendPbcArray_LSB 0x12
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendPbcArray_MSB 0x12
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendPbcArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufExtra_LSB 0x11
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufExtra_MSB 0x11
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufExtra_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufMain_LSB 0x10
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufMain_MSB 0x10
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufMain_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufVL15_LSB 0xF
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufVL15_MSB 0xF
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearSendBufVL15_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvEgrArray_LSB 0xB
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvEgrArray_MSB 0xB
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvEgrArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvTIDArray_LSB 0xA
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvTIDArray_MSB 0xA
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvTIDArray_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvFlags_1_LSB 0x6
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvFlags_1_MSB 0x6
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvFlags_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvBuf_1_LSB 0x5
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvBuf_1_MSB 0x5
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvBuf_1_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvFlags_0_LSB 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvFlags_0_MSB 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvFlags_0_RMASK 0x1
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvBuf_0_LSB 0x0
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvBuf_0_MSB 0x0
#define QIB_7322_MemMultiUnCorErrClear_MulUncErrClearRcvBuf_0_RMASK 0x1

#define QIB_7322_MemUnCorErrMask_OFFS 0x628
#define QIB_7322_MemUnCorErrMask_DEF 0x0000000000000000
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable2_LSB 0x37
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable2_MSB 0x37
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable2_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable1_LSB 0x36
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable1_MSB 0x36
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable0_LSB 0x35
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable0_MSB 0x35
#define QIB_7322_MemUnCorErrMask_UncErrMskMsixTable0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemUnCorErrMask_UncErrMskPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemUnCorErrMask_UncErrMskSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemUnCorErrMask_UncErrMskSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemUnCorErrMask_UncErrMskSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemUnCorErrMask_UncErrMskSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemUnCorErrMask_UncErrMskSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendPbcArray_LSB 0x12
#define QIB_7322_MemUnCorErrMask_UncErrMskSendPbcArray_MSB 0x12
#define QIB_7322_MemUnCorErrMask_UncErrMskSendPbcArray_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufExtra_LSB 0x11
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufExtra_MSB 0x11
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufExtra_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufMain_LSB 0x10
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufMain_MSB 0x10
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufMain_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufVL15_LSB 0xF
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufVL15_MSB 0xF
#define QIB_7322_MemUnCorErrMask_UncErrMskSendBufVL15_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvEgrArray_LSB 0xB
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvEgrArray_MSB 0xB
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvEgrArray_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvTIDArray_LSB 0xA
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvTIDArray_MSB 0xA
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvTIDArray_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemUnCorErrMask_UncErrMskLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemUnCorErrMask_UncErrMskLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvFlags_1_LSB 0x6
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvFlags_1_MSB 0x6
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvFlags_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvBuf_1_LSB 0x5
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvBuf_1_MSB 0x5
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemUnCorErrMask_UncErrMskLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemUnCorErrMask_UncErrMskLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvFlags_0_LSB 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvFlags_0_MSB 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvFlags_0_RMASK 0x1
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvBuf_0_LSB 0x0
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvBuf_0_MSB 0x0
#define QIB_7322_MemUnCorErrMask_UncErrMskRcvBuf_0_RMASK 0x1

#define QIB_7322_MemUnCorErrStatus_OFFS 0x630
#define QIB_7322_MemUnCorErrStatus_DEF 0x0000000000000000
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable2_LSB 0x37
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable2_MSB 0x37
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable2_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable1_LSB 0x36
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable1_MSB 0x36
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable0_LSB 0x35
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable0_MSB 0x35
#define QIB_7322_MemUnCorErrStatus_UncErrStatusMsixTable0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemUnCorErrStatus_UncErrStatusPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendPbcArray_LSB 0x12
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendPbcArray_MSB 0x12
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendPbcArray_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufExtra_LSB 0x11
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufExtra_MSB 0x11
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufExtra_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufMain_LSB 0x10
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufMain_MSB 0x10
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufMain_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufVL15_LSB 0xF
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufVL15_MSB 0xF
#define QIB_7322_MemUnCorErrStatus_UncErrStatusSendBufVL15_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvEgrArray_LSB 0xB
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvEgrArray_MSB 0xB
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvEgrArray_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvTIDArray_LSB 0xA
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvTIDArray_MSB 0xA
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvTIDArray_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemUnCorErrStatus_UncErrStatusLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemUnCorErrStatus_UncErrStatusLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvFlags_1_LSB 0x6
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvFlags_1_MSB 0x6
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvFlags_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvBuf_1_LSB 0x5
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvBuf_1_MSB 0x5
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemUnCorErrStatus_UncErrStatusLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemUnCorErrStatus_UncErrStatusLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvFlags_0_LSB 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvFlags_0_MSB 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvFlags_0_RMASK 0x1
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvBuf_0_LSB 0x0
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvBuf_0_MSB 0x0
#define QIB_7322_MemUnCorErrStatus_UncErrStatusRcvBuf_0_RMASK 0x1

#define QIB_7322_MemUnCorErrClear_OFFS 0x638
#define QIB_7322_MemUnCorErrClear_DEF 0x0000000000000000
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable2_LSB 0x37
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable2_MSB 0x37
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable2_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable1_LSB 0x36
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable1_MSB 0x36
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable0_LSB 0x35
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable0_MSB 0x35
#define QIB_7322_MemUnCorErrClear_UncErrClearMsixTable0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemUnCorErrClear_UncErrClearPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemUnCorErrClear_UncErrClearSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemUnCorErrClear_UncErrClearSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemUnCorErrClear_UncErrClearSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemUnCorErrClear_UncErrClearSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemUnCorErrClear_UncErrClearSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendPbcArray_LSB 0x12
#define QIB_7322_MemUnCorErrClear_UncErrClearSendPbcArray_MSB 0x12
#define QIB_7322_MemUnCorErrClear_UncErrClearSendPbcArray_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufExtra_LSB 0x11
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufExtra_MSB 0x11
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufExtra_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufMain_LSB 0x10
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufMain_MSB 0x10
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufMain_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufVL15_LSB 0xF
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufVL15_MSB 0xF
#define QIB_7322_MemUnCorErrClear_UncErrClearSendBufVL15_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvEgrArray_LSB 0xB
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvEgrArray_MSB 0xB
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvEgrArray_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvTIDArray_LSB 0xA
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvTIDArray_MSB 0xA
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvTIDArray_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemUnCorErrClear_UncErrClearLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemUnCorErrClear_UncErrClearLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvFlags_1_LSB 0x6
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvFlags_1_MSB 0x6
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvFlags_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvBuf_1_LSB 0x5
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvBuf_1_MSB 0x5
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvBuf_1_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemUnCorErrClear_UncErrClearLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemUnCorErrClear_UncErrClearLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvFlags_0_LSB 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvFlags_0_MSB 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvFlags_0_RMASK 0x1
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvBuf_0_LSB 0x0
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvBuf_0_MSB 0x0
#define QIB_7322_MemUnCorErrClear_UncErrClearRcvBuf_0_RMASK 0x1

#define QIB_7322_MemMultiCorErrMask_OFFS 0x640
#define QIB_7322_MemMultiCorErrMask_DEF 0x0000000000000000
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable2_LSB 0x37
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable2_MSB 0x37
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable2_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable1_LSB 0x36
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable1_MSB 0x36
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable0_LSB 0x35
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable0_MSB 0x35
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskMsixTable0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendPbcArray_LSB 0x12
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendPbcArray_MSB 0x12
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendPbcArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufExtra_LSB 0x11
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufExtra_MSB 0x11
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufExtra_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufMain_LSB 0x10
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufMain_MSB 0x10
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufMain_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufVL15_LSB 0xF
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufVL15_MSB 0xF
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskSendBufVL15_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvEgrArray_LSB 0xB
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvEgrArray_MSB 0xB
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvEgrArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvTIDArray_LSB 0xA
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvTIDArray_MSB 0xA
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvTIDArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvFlags_1_LSB 0x6
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvFlags_1_MSB 0x6
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvFlags_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvBuf_1_LSB 0x5
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvBuf_1_MSB 0x5
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvFlags_0_LSB 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvFlags_0_MSB 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvFlags_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvBuf_0_LSB 0x0
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvBuf_0_MSB 0x0
#define QIB_7322_MemMultiCorErrMask_MulCorErrMskRcvBuf_0_RMASK 0x1

#define QIB_7322_MemMultiCorErrStatus_OFFS 0x648
#define QIB_7322_MemMultiCorErrStatus_DEF 0x0000000000000000
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable2_LSB 0x37
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable2_MSB 0x37
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable2_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable1_LSB 0x36
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable1_MSB 0x36
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable0_LSB 0x35
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable0_MSB 0x35
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusMsixTable0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendPbcArray_LSB 0x12
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendPbcArray_MSB 0x12
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendPbcArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufExtra_LSB 0x11
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufExtra_MSB 0x11
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufExtra_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufMain_LSB 0x10
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufMain_MSB 0x10
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufMain_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufVL15_LSB 0xF
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufVL15_MSB 0xF
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusSendBufVL15_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvEgrArray_LSB 0xB
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvEgrArray_MSB 0xB
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvEgrArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvTIDArray_LSB 0xA
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvTIDArray_MSB 0xA
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvTIDArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvFlags_1_LSB 0x6
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvFlags_1_MSB 0x6
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvFlags_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvBuf_1_LSB 0x5
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvBuf_1_MSB 0x5
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvFlags_0_LSB 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvFlags_0_MSB 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvFlags_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvBuf_0_LSB 0x0
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvBuf_0_MSB 0x0
#define QIB_7322_MemMultiCorErrStatus_MulCorErrStatusRcvBuf_0_RMASK 0x1

#define QIB_7322_MemMultiCorErrClear_OFFS 0x650
#define QIB_7322_MemMultiCorErrClear_DEF 0x0000000000000000
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable2_LSB 0x37
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable2_MSB 0x37
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable2_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable1_LSB 0x36
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable1_MSB 0x36
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable0_LSB 0x35
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable0_MSB 0x35
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearMsixTable0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendPbcArray_LSB 0x12
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendPbcArray_MSB 0x12
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendPbcArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufExtra_LSB 0x11
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufExtra_MSB 0x11
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufExtra_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufMain_LSB 0x10
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufMain_MSB 0x10
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufMain_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufVL15_LSB 0xF
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufVL15_MSB 0xF
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearSendBufVL15_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvEgrArray_LSB 0xB
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvEgrArray_MSB 0xB
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvEgrArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvTIDArray_LSB 0xA
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvTIDArray_MSB 0xA
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvTIDArray_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvFlags_1_LSB 0x6
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvFlags_1_MSB 0x6
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvFlags_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvBuf_1_LSB 0x5
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvBuf_1_MSB 0x5
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvBuf_1_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvFlags_0_LSB 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvFlags_0_MSB 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvFlags_0_RMASK 0x1
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvBuf_0_LSB 0x0
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvBuf_0_MSB 0x0
#define QIB_7322_MemMultiCorErrClear_MulCorErrClearRcvBuf_0_RMASK 0x1

#define QIB_7322_MemCorErrMask_OFFS 0x658
#define QIB_7322_MemCorErrMask_DEF 0x0000000000000000
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable2_LSB 0x37
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable2_MSB 0x37
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable2_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable1_LSB 0x36
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable1_MSB 0x36
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable0_LSB 0x35
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable0_MSB 0x35
#define QIB_7322_MemCorErrMask_CorErrMskMsixTable0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemCorErrMask_CorErrMskPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemCorErrMask_CorErrMskPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemCorErrMask_CorErrMskPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemCorErrMask_CorErrMskPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemCorErrMask_CorErrMskPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemCorErrMask_CorErrMskPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemCorErrMask_CorErrMskPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemCorErrMask_CorErrMskPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemCorErrMask_CorErrMskPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemCorErrMask_CorErrMskPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemCorErrMask_CorErrMskSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemCorErrMask_CorErrMskSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemCorErrMask_CorErrMskSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemCorErrMask_CorErrMskSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemCorErrMask_CorErrMskSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendPbcArray_LSB 0x12
#define QIB_7322_MemCorErrMask_CorErrMskSendPbcArray_MSB 0x12
#define QIB_7322_MemCorErrMask_CorErrMskSendPbcArray_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendBufExtra_LSB 0x11
#define QIB_7322_MemCorErrMask_CorErrMskSendBufExtra_MSB 0x11
#define QIB_7322_MemCorErrMask_CorErrMskSendBufExtra_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendBufMain_LSB 0x10
#define QIB_7322_MemCorErrMask_CorErrMskSendBufMain_MSB 0x10
#define QIB_7322_MemCorErrMask_CorErrMskSendBufMain_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskSendBufVL15_LSB 0xF
#define QIB_7322_MemCorErrMask_CorErrMskSendBufVL15_MSB 0xF
#define QIB_7322_MemCorErrMask_CorErrMskSendBufVL15_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvEgrArray_LSB 0xB
#define QIB_7322_MemCorErrMask_CorErrMskRcvEgrArray_MSB 0xB
#define QIB_7322_MemCorErrMask_CorErrMskRcvEgrArray_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvTIDArray_LSB 0xA
#define QIB_7322_MemCorErrMask_CorErrMskRcvTIDArray_MSB 0xA
#define QIB_7322_MemCorErrMask_CorErrMskRcvTIDArray_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemCorErrMask_CorErrMskLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemCorErrMask_CorErrMskLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvFlags_1_LSB 0x6
#define QIB_7322_MemCorErrMask_CorErrMskRcvFlags_1_MSB 0x6
#define QIB_7322_MemCorErrMask_CorErrMskRcvFlags_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvBuf_1_LSB 0x5
#define QIB_7322_MemCorErrMask_CorErrMskRcvBuf_1_MSB 0x5
#define QIB_7322_MemCorErrMask_CorErrMskRcvBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemCorErrMask_CorErrMskRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemCorErrMask_CorErrMskLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemCorErrMask_CorErrMskLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvFlags_0_LSB 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvFlags_0_MSB 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvFlags_0_RMASK 0x1
#define QIB_7322_MemCorErrMask_CorErrMskRcvBuf_0_LSB 0x0
#define QIB_7322_MemCorErrMask_CorErrMskRcvBuf_0_MSB 0x0
#define QIB_7322_MemCorErrMask_CorErrMskRcvBuf_0_RMASK 0x1

#define QIB_7322_MemCorErrStatus_OFFS 0x660
#define QIB_7322_MemCorErrStatus_DEF 0x0000000000000000
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable2_LSB 0x37
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable2_MSB 0x37
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable2_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable1_LSB 0x36
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable1_MSB 0x36
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable0_LSB 0x35
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable0_MSB 0x35
#define QIB_7322_MemCorErrStatus_CorErrStatusMsixTable0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemCorErrStatus_CorErrStatusPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemCorErrStatus_CorErrStatusSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemCorErrStatus_CorErrStatusSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemCorErrStatus_CorErrStatusSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemCorErrStatus_CorErrStatusSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemCorErrStatus_CorErrStatusSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendPbcArray_LSB 0x12
#define QIB_7322_MemCorErrStatus_CorErrStatusSendPbcArray_MSB 0x12
#define QIB_7322_MemCorErrStatus_CorErrStatusSendPbcArray_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufExtra_LSB 0x11
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufExtra_MSB 0x11
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufExtra_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufMain_LSB 0x10
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufMain_MSB 0x10
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufMain_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufVL15_LSB 0xF
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufVL15_MSB 0xF
#define QIB_7322_MemCorErrStatus_CorErrStatusSendBufVL15_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvEgrArray_LSB 0xB
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvEgrArray_MSB 0xB
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvEgrArray_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvTIDArray_LSB 0xA
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvTIDArray_MSB 0xA
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvTIDArray_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemCorErrStatus_CorErrStatusLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemCorErrStatus_CorErrStatusLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvFlags_1_LSB 0x6
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvFlags_1_MSB 0x6
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvFlags_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvBuf_1_LSB 0x5
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvBuf_1_MSB 0x5
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemCorErrStatus_CorErrStatusLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemCorErrStatus_CorErrStatusLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvFlags_0_LSB 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvFlags_0_MSB 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvFlags_0_RMASK 0x1
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvBuf_0_LSB 0x0
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvBuf_0_MSB 0x0
#define QIB_7322_MemCorErrStatus_CorErrStatusRcvBuf_0_RMASK 0x1

#define QIB_7322_MemCorErrClear_OFFS 0x668
#define QIB_7322_MemCorErrClear_DEF 0x0000000000000000
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable2_LSB 0x37
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable2_MSB 0x37
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable2_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable1_LSB 0x36
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable1_MSB 0x36
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable0_LSB 0x35
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable0_MSB 0x35
#define QIB_7322_MemCorErrClear_CorErrClearMsixTable0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearPCIeCompDataBuf_LSB 0x34
#define QIB_7322_MemCorErrClear_CorErrClearPCIeCompDataBuf_MSB 0x34
#define QIB_7322_MemCorErrClear_CorErrClearPCIeCompDataBuf_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearPCIeCompHdrBuf_LSB 0x33
#define QIB_7322_MemCorErrClear_CorErrClearPCIeCompHdrBuf_MSB 0x33
#define QIB_7322_MemCorErrClear_CorErrClearPCIeCompHdrBuf_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearPCIePostDataBuf_LSB 0x32
#define QIB_7322_MemCorErrClear_CorErrClearPCIePostDataBuf_MSB 0x32
#define QIB_7322_MemCorErrClear_CorErrClearPCIePostDataBuf_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearPCIePostHdrBuf_LSB 0x31
#define QIB_7322_MemCorErrClear_CorErrClearPCIePostHdrBuf_MSB 0x31
#define QIB_7322_MemCorErrClear_CorErrClearPCIePostHdrBuf_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearPCIeRetryBuf_LSB 0x30
#define QIB_7322_MemCorErrClear_CorErrClearPCIeRetryBuf_MSB 0x30
#define QIB_7322_MemCorErrClear_CorErrClearPCIeRetryBuf_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendRmFIFO_1_LSB 0x24
#define QIB_7322_MemCorErrClear_CorErrClearSendRmFIFO_1_MSB 0x24
#define QIB_7322_MemCorErrClear_CorErrClearSendRmFIFO_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendRmFIFO_0_LSB 0x23
#define QIB_7322_MemCorErrClear_CorErrClearSendRmFIFO_0_MSB 0x23
#define QIB_7322_MemCorErrClear_CorErrClearSendRmFIFO_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO7_1_LSB 0x22
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO7_1_MSB 0x22
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO7_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO6_1_LSB 0x21
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO6_1_MSB 0x21
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO6_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO5_1_LSB 0x20
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO5_1_MSB 0x20
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO5_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO4_1_LSB 0x1F
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO4_1_MSB 0x1F
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO4_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO3_1_LSB 0x1E
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO3_1_MSB 0x1E
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO3_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO2_1_LSB 0x1D
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO2_1_MSB 0x1D
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO2_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO1_1_LSB 0x1C
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO1_1_MSB 0x1C
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO1_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO0_1_LSB 0x1B
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO0_1_MSB 0x1B
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO0_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO7_0_LSB 0x1A
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO7_0_MSB 0x1A
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO7_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO6_0_LSB 0x19
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO6_0_MSB 0x19
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO6_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO5_0_LSB 0x18
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO5_0_MSB 0x18
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO5_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO4_0_LSB 0x17
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO4_0_MSB 0x17
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO4_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO3_0_LSB 0x16
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO3_0_MSB 0x16
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO3_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO2_0_LSB 0x15
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO2_0_MSB 0x15
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO2_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO1_0_LSB 0x14
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO1_0_MSB 0x14
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO1_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO0_0_LSB 0x13
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO0_0_MSB 0x13
#define QIB_7322_MemCorErrClear_CorErrClearSendLaFIFO0_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendPbcArray_LSB 0x12
#define QIB_7322_MemCorErrClear_CorErrClearSendPbcArray_MSB 0x12
#define QIB_7322_MemCorErrClear_CorErrClearSendPbcArray_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendBufExtra_LSB 0x11
#define QIB_7322_MemCorErrClear_CorErrClearSendBufExtra_MSB 0x11
#define QIB_7322_MemCorErrClear_CorErrClearSendBufExtra_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendBufMain_LSB 0x10
#define QIB_7322_MemCorErrClear_CorErrClearSendBufMain_MSB 0x10
#define QIB_7322_MemCorErrClear_CorErrClearSendBufMain_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearSendBufVL15_LSB 0xF
#define QIB_7322_MemCorErrClear_CorErrClearSendBufVL15_MSB 0xF
#define QIB_7322_MemCorErrClear_CorErrClearSendBufVL15_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvEgrArray_LSB 0xB
#define QIB_7322_MemCorErrClear_CorErrClearRcvEgrArray_MSB 0xB
#define QIB_7322_MemCorErrClear_CorErrClearRcvEgrArray_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvTIDArray_LSB 0xA
#define QIB_7322_MemCorErrClear_CorErrClearRcvTIDArray_MSB 0xA
#define QIB_7322_MemCorErrClear_CorErrClearRcvTIDArray_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMADataBuf_1_LSB 0x9
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMADataBuf_1_MSB 0x9
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMADataBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMAHdrBuf_1_LSB 0x8
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMAHdrBuf_1_MSB 0x8
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMAHdrBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearLookupiqBuf_1_LSB 0x7
#define QIB_7322_MemCorErrClear_CorErrClearLookupiqBuf_1_MSB 0x7
#define QIB_7322_MemCorErrClear_CorErrClearLookupiqBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvFlags_1_LSB 0x6
#define QIB_7322_MemCorErrClear_CorErrClearRcvFlags_1_MSB 0x6
#define QIB_7322_MemCorErrClear_CorErrClearRcvFlags_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvBuf_1_LSB 0x5
#define QIB_7322_MemCorErrClear_CorErrClearRcvBuf_1_MSB 0x5
#define QIB_7322_MemCorErrClear_CorErrClearRcvBuf_1_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMADataBuf_0_LSB 0x4
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMADataBuf_0_MSB 0x4
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMADataBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMAHdrBuf_0_LSB 0x3
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMAHdrBuf_0_MSB 0x3
#define QIB_7322_MemCorErrClear_CorErrClearRcvDMAHdrBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearLookupiqBuf_0_LSB 0x2
#define QIB_7322_MemCorErrClear_CorErrClearLookupiqBuf_0_MSB 0x2
#define QIB_7322_MemCorErrClear_CorErrClearLookupiqBuf_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvFlags_0_LSB 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvFlags_0_MSB 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvFlags_0_RMASK 0x1
#define QIB_7322_MemCorErrClear_CorErrClearRcvBuf_0_LSB 0x0
#define QIB_7322_MemCorErrClear_CorErrClearRcvBuf_0_MSB 0x0
#define QIB_7322_MemCorErrClear_CorErrClearRcvBuf_0_RMASK 0x1

#define QIB_7322_MsixTableUnCorErrLogA_OFFS 0x680
#define QIB_7322_MsixTableUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_MsixTableUnCorErrLogA_MsixTable_1_0_UnCorErrData_LSB 0x0
#define QIB_7322_MsixTableUnCorErrLogA_MsixTable_1_0_UnCorErrData_MSB 0x3F
#define QIB_7322_MsixTableUnCorErrLogA_MsixTable_1_0_UnCorErrData_RMASK 0x0

#define QIB_7322_MsixTableUnCorErrLogB_OFFS 0x688
#define QIB_7322_MsixTableUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_2_UnCorErrCheckBits_LSB 0x2E
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_2_UnCorErrCheckBits_MSB 0x34
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_2_UnCorErrCheckBits_RMASK 0x7F
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_1_UnCorErrCheckBits_LSB 0x27
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_1_UnCorErrCheckBits_MSB 0x2D
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_1_UnCorErrCheckBits_RMASK 0x7F
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_0_UnCorErrCheckBits_LSB 0x20
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_0_UnCorErrCheckBits_MSB 0x26
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_0_UnCorErrCheckBits_RMASK 0x7F
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_2_UnCorErrData_LSB 0x0
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_2_UnCorErrData_MSB 0x1F
#define QIB_7322_MsixTableUnCorErrLogB_MsixTable_2_UnCorErrData_RMASK 0xFFFFFFFF

#define QIB_7322_MsixTableUnCorErrLogC_OFFS 0x690
#define QIB_7322_MsixTableUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_2_UnCorErrAddr_LSB 0xE
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_2_UnCorErrAddr_MSB 0x14
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_2_UnCorErrAddr_RMASK 0x7F
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_1_UnCorErrAddr_LSB 0x7
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_1_UnCorErrAddr_MSB 0xD
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_1_UnCorErrAddr_RMASK 0x7F
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_0_UnCorErrAddr_LSB 0x0
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_0_UnCorErrAddr_MSB 0x6
#define QIB_7322_MsixTableUnCorErrLogC_MsixTable_0_UnCorErrAddr_RMASK 0x7F

#define QIB_7322_MsixEntryWithUncorErr_OFFS 0x698
#define QIB_7322_MsixEntryWithUncorErr_DEF 0x0000000000000000

#define QIB_7322_MsixTableCorErrLogA_OFFS 0x6A0
#define QIB_7322_MsixTableCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_MsixTableCorErrLogA_MsixTable_1_0_CorErrData_LSB 0x0
#define QIB_7322_MsixTableCorErrLogA_MsixTable_1_0_CorErrData_MSB 0x3F
#define QIB_7322_MsixTableCorErrLogA_MsixTable_1_0_CorErrData_RMASK 0x0

#define QIB_7322_MsixTableCorErrLogB_OFFS 0x6A8
#define QIB_7322_MsixTableCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_MsixTableCorErrLogB_MsixTable_2_CorErrCheckBits_LSB 0x2E
#define QIB_7322_MsixTableCorErrLogB_MsixTable_2_CorErrCheckBits_MSB 0x34
#define QIB_7322_MsixTableCorErrLogB_MsixTable_2_CorErrCheckBits_RMASK 0x7F
#define QIB_7322_MsixTableCorErrLogB_MsixTable_1_CorErrCheckBits_LSB 0x27
#define QIB_7322_MsixTableCorErrLogB_MsixTable_1_CorErrCheckBits_MSB 0x2D
#define QIB_7322_MsixTableCorErrLogB_MsixTable_1_CorErrCheckBits_RMASK 0x7F
#define QIB_7322_MsixTableCorErrLogB_MsixTable_0_CorErrCheckBits_LSB 0x20
#define QIB_7322_MsixTableCorErrLogB_MsixTable_0_CorErrCheckBits_MSB 0x26
#define QIB_7322_MsixTableCorErrLogB_MsixTable_0_CorErrCheckBits_RMASK 0x7F
#define QIB_7322_MsixTableCorErrLogB_MsixTable_2_CorErrData_LSB 0x0
#define QIB_7322_MsixTableCorErrLogB_MsixTable_2_CorErrData_MSB 0x1F
#define QIB_7322_MsixTableCorErrLogB_MsixTable_2_CorErrData_RMASK 0xFFFFFFFF

#define QIB_7322_MsixTableCorErrLogC_OFFS 0x6B0
#define QIB_7322_MsixTableCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_MsixTableCorErrLogC_MsixTable_2_CorErrAddr_LSB 0xE
#define QIB_7322_MsixTableCorErrLogC_MsixTable_2_CorErrAddr_MSB 0x14
#define QIB_7322_MsixTableCorErrLogC_MsixTable_2_CorErrAddr_RMASK 0x7F
#define QIB_7322_MsixTableCorErrLogC_MsixTable_1_CorErrAddr_LSB 0x7
#define QIB_7322_MsixTableCorErrLogC_MsixTable_1_CorErrAddr_MSB 0xD
#define QIB_7322_MsixTableCorErrLogC_MsixTable_1_CorErrAddr_RMASK 0x7F
#define QIB_7322_MsixTableCorErrLogC_MsixTable_0_CorErrAddr_LSB 0x0
#define QIB_7322_MsixTableCorErrLogC_MsixTable_0_CorErrAddr_MSB 0x6
#define QIB_7322_MsixTableCorErrLogC_MsixTable_0_CorErrAddr_RMASK 0x7F

#define QIB_7322_PcieCplDataBufrUnCorErrLogA_OFFS 0x700
#define QIB_7322_PcieCplDataBufrUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PcieCplDataBufrUnCorErrLogA_PcieCplDataBufrUnCorErrData_63_0_LSB 0x0
#define QIB_7322_PcieCplDataBufrUnCorErrLogA_PcieCplDataBufrUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_PcieCplDataBufrUnCorErrLogA_PcieCplDataBufrUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_PcieCplDataBufrUnCorErrLogB_OFFS 0x708
#define QIB_7322_PcieCplDataBufrUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PcieCplDataBufrUnCorErrLogB_PcieCplDataBufrUnCorErrData_127_64_LSB 0x0
#define QIB_7322_PcieCplDataBufrUnCorErrLogB_PcieCplDataBufrUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_PcieCplDataBufrUnCorErrLogB_PcieCplDataBufrUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_PcieCplDataBufrUnCorErrLogC_OFFS 0x710
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrAddr_13_0_LSB 0x1F
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrAddr_13_0_MSB 0x2C
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrCheckBit_21_0_LSB 0x9
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrCheckBit_21_0_MSB 0x1E
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrCheckBit_21_0_RMASK 0x3FFFFF
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrData_136_128_LSB 0x0
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrData_136_128_MSB 0x8
#define QIB_7322_PcieCplDataBufrUnCorErrLogC_PcieCplDataBufrUnCorErrData_136_128_RMASK 0x1FF

#define QIB_7322_PcieCplHdrBufrUnCorErrLogA_OFFS 0x720
#define QIB_7322_PcieCplHdrBufrUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PcieCplHdrBufrUnCorErrLogA_PcieCplHdrBufrUnCorErrHdr_63_0_LSB 0x0
#define QIB_7322_PcieCplHdrBufrUnCorErrLogA_PcieCplHdrBufrUnCorErrHdr_63_0_MSB 0x3F
#define QIB_7322_PcieCplHdrBufrUnCorErrLogA_PcieCplHdrBufrUnCorErrHdr_63_0_RMASK 0x0

#define QIB_7322_PcieCplHdrBufrUnCorErrLogB_OFFS 0x728
#define QIB_7322_PcieCplHdrBufrUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PcieCplHdrBufrUnCorErrLogB_PcieCplHdrBufrUnCorErrHdr_103_64_LSB 0x0
#define QIB_7322_PcieCplHdrBufrUnCorErrLogB_PcieCplHdrBufrUnCorErrHdr_103_64_MSB 0x27
#define QIB_7322_PcieCplHdrBufrUnCorErrLogB_PcieCplHdrBufrUnCorErrHdr_103_64_RMASK 0xFFFFFFFFFF

#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_OFFS 0x730
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_PcieCplHdrBufrUnCorErrAddr_8_0_LSB 0x10
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_PcieCplHdrBufrUnCorErrAddr_8_0_MSB 0x18
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_PcieCplHdrBufrUnCorErrAddr_8_0_RMASK 0x1FF
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_PcieCplHdrBufrUnCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_PcieCplHdrBufrUnCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_PcieCplHdrBufrUnCorErrLogC_PcieCplHdrBufrUnCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_PciePDataBufrUnCorErrLogA_OFFS 0x740
#define QIB_7322_PciePDataBufrUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PciePDataBufrUnCorErrLogA_PciePDataBufrUnCorErrData_63_0_LSB 0x0
#define QIB_7322_PciePDataBufrUnCorErrLogA_PciePDataBufrUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_PciePDataBufrUnCorErrLogA_PciePDataBufrUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_PciePDataBufrUnCorErrLogB_OFFS 0x748
#define QIB_7322_PciePDataBufrUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PciePDataBufrUnCorErrLogB_PciePDataBufrUnCorErrData_127_64_LSB 0x0
#define QIB_7322_PciePDataBufrUnCorErrLogB_PciePDataBufrUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_PciePDataBufrUnCorErrLogB_PciePDataBufrUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_PciePDataBufrUnCorErrLogC_OFFS 0x750
#define QIB_7322_PciePDataBufrUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrAddr_13_0_LSB 0x1F
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrAddr_13_0_MSB 0x2C
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrCheckBit_21_0_LSB 0x9
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrCheckBit_21_0_MSB 0x1E
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrCheckBit_21_0_RMASK 0x3FFFFF
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrData_136_128_LSB 0x0
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrData_136_128_MSB 0x8
#define QIB_7322_PciePDataBufrUnCorErrLogC_PciePDataBufrUnCorErrData_136_128_RMASK 0x1FF

#define QIB_7322_PciePHdrBufrUnCorErrLogA_OFFS 0x760
#define QIB_7322_PciePHdrBufrUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PciePHdrBufrUnCorErrLogA_PciePHdrBufrUnCorErrData_63_0_LSB 0x0
#define QIB_7322_PciePHdrBufrUnCorErrLogA_PciePHdrBufrUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_PciePHdrBufrUnCorErrLogA_PciePHdrBufrUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_PciePHdrBufrUnCorErrLogB_OFFS 0x768
#define QIB_7322_PciePHdrBufrUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PciePHdrBufrUnCorErrLogB_PciePHdrBufrUnCorErrData_107_64_LSB 0x0
#define QIB_7322_PciePHdrBufrUnCorErrLogB_PciePHdrBufrUnCorErrData_107_64_MSB 0x2B
#define QIB_7322_PciePHdrBufrUnCorErrLogB_PciePHdrBufrUnCorErrData_107_64_RMASK 0xFFFFFFFFFFF

#define QIB_7322_PciePHdrBufrUnCorErrLogC_OFFS 0x770
#define QIB_7322_PciePHdrBufrUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PciePHdrBufrUnCorErrLogC_PciePHdrBufrUnCorErrAddr_8_0_LSB 0x10
#define QIB_7322_PciePHdrBufrUnCorErrLogC_PciePHdrBufrUnCorErrAddr_8_0_MSB 0x18
#define QIB_7322_PciePHdrBufrUnCorErrLogC_PciePHdrBufrUnCorErrAddr_8_0_RMASK 0x1FF
#define QIB_7322_PciePHdrBufrUnCorErrLogC_PciePHdrBufrUnCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_PciePHdrBufrUnCorErrLogC_PciePHdrBufrUnCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_PciePHdrBufrUnCorErrLogC_PciePHdrBufrUnCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_PcieRetryBufrUnCorErrLogA_OFFS 0x780
#define QIB_7322_PcieRetryBufrUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PcieRetryBufrUnCorErrLogA_PcieRetryBufrUnCorErrData_63_0_LSB 0x0
#define QIB_7322_PcieRetryBufrUnCorErrLogA_PcieRetryBufrUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_PcieRetryBufrUnCorErrLogA_PcieRetryBufrUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_PcieRetryBufrUnCorErrLogB_OFFS 0x788
#define QIB_7322_PcieRetryBufrUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PcieRetryBufrUnCorErrLogB_PcieRetryBufrUnCorErrData_127_64_LSB 0x0
#define QIB_7322_PcieRetryBufrUnCorErrLogB_PcieRetryBufrUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_PcieRetryBufrUnCorErrLogB_PcieRetryBufrUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_PcieRetryBufrUnCorErrLogC_OFFS 0x790
#define QIB_7322_PcieRetryBufrUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrAddr_13_0_LSB 0x1B
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrAddr_13_0_MSB 0x28
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrCheckBit_20_0_LSB 0x6
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrCheckBit_20_0_MSB 0x1A
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrCheckBit_20_0_RMASK 0x1FFFFF
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrData_133_128_LSB 0x0
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrData_133_128_MSB 0x5
#define QIB_7322_PcieRetryBufrUnCorErrLogC_PcieRetryBufrUnCorErrData_133_128_RMASK 0x3F

#define QIB_7322_RxTIDArrayUnCorErrLogA_OFFS 0x800
#define QIB_7322_RxTIDArrayUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_RxTIDArrayUnCorErrLogA_RxTIDArrayUnCorErrCheckBit_11_0_LSB 0x28
#define QIB_7322_RxTIDArrayUnCorErrLogA_RxTIDArrayUnCorErrCheckBit_11_0_MSB 0x33
#define QIB_7322_RxTIDArrayUnCorErrLogA_RxTIDArrayUnCorErrCheckBit_11_0_RMASK 0xFFF
#define QIB_7322_RxTIDArrayUnCorErrLogA_RxTIDArrayUnCorErrData_39_0_LSB 0x0
#define QIB_7322_RxTIDArrayUnCorErrLogA_RxTIDArrayUnCorErrData_39_0_MSB 0x27
#define QIB_7322_RxTIDArrayUnCorErrLogA_RxTIDArrayUnCorErrData_39_0_RMASK 0xFFFFFFFFFF

#define QIB_7322_RxTIDArrayUnCorErrLogB_OFFS 0x808
#define QIB_7322_RxTIDArrayUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_RxTIDArrayUnCorErrLogB_RxTIDArrayUnCorErrAddr_16_0_LSB 0x0
#define QIB_7322_RxTIDArrayUnCorErrLogB_RxTIDArrayUnCorErrAddr_16_0_MSB 0x10
#define QIB_7322_RxTIDArrayUnCorErrLogB_RxTIDArrayUnCorErrAddr_16_0_RMASK 0x1FFFF

#define QIB_7322_RxEagerArrayUnCorErrLogA_OFFS 0x810
#define QIB_7322_RxEagerArrayUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_RxEagerArrayUnCorErrLogA_RxEagerArrayUnCorErrCheckBit_11_0_LSB 0x28
#define QIB_7322_RxEagerArrayUnCorErrLogA_RxEagerArrayUnCorErrCheckBit_11_0_MSB 0x33
#define QIB_7322_RxEagerArrayUnCorErrLogA_RxEagerArrayUnCorErrCheckBit_11_0_RMASK 0xFFF
#define QIB_7322_RxEagerArrayUnCorErrLogA_RxEagerArrayUnCorErrData_39_0_LSB 0x0
#define QIB_7322_RxEagerArrayUnCorErrLogA_RxEagerArrayUnCorErrData_39_0_MSB 0x27
#define QIB_7322_RxEagerArrayUnCorErrLogA_RxEagerArrayUnCorErrData_39_0_RMASK 0xFFFFFFFFFF

#define QIB_7322_RxEagerArrayUnCorErrLogB_OFFS 0x818
#define QIB_7322_RxEagerArrayUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_RxEagerArrayUnCorErrLogB_RxEagerArrayUnCorErrAddr_17_0_LSB 0x0
#define QIB_7322_RxEagerArrayUnCorErrLogB_RxEagerArrayUnCorErrAddr_17_0_MSB 0x11
#define QIB_7322_RxEagerArrayUnCorErrLogB_RxEagerArrayUnCorErrAddr_17_0_RMASK 0x3FFFF

#define QIB_7322_SBufMainArrayUnCorErrLogA_OFFS 0x880
#define QIB_7322_SBufMainArrayUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_SBufMainArrayUnCorErrLogA_SBufMainArrayUnCorErrData_63_0_LSB 0x0
#define QIB_7322_SBufMainArrayUnCorErrLogA_SBufMainArrayUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_SBufMainArrayUnCorErrLogA_SBufMainArrayUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_SBufMainArrayUnCorErrLogB_OFFS 0x888
#define QIB_7322_SBufMainArrayUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_SBufMainArrayUnCorErrLogB_SBufMainArrayUnCorErrData_127_64_LSB 0x0
#define QIB_7322_SBufMainArrayUnCorErrLogB_SBufMainArrayUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_SBufMainArrayUnCorErrLogB_SBufMainArrayUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_SBufMainArrayUnCorErrLogC_OFFS 0x890
#define QIB_7322_SBufMainArrayUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrDword_3_0_LSB 0x3C
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrDword_3_0_MSB 0x3F
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrDword_3_0_RMASK 0xF
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrAddr_18_0_LSB 0x1C
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrAddr_18_0_MSB 0x2E
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrAddr_18_0_RMASK 0x7FFFF
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_SBufMainArrayUnCorErrLogC_SBufMainArrayUnCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_SBufExtraArrayUnCorErrLogA_OFFS 0x898
#define QIB_7322_SBufExtraArrayUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_SBufExtraArrayUnCorErrLogA_SBufExtraArrayUnCorErrData_63_0_LSB 0x0
#define QIB_7322_SBufExtraArrayUnCorErrLogA_SBufExtraArrayUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_SBufExtraArrayUnCorErrLogA_SBufExtraArrayUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_SBufExtraArrayUnCorErrLogB_OFFS 0x8A0
#define QIB_7322_SBufExtraArrayUnCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_SBufExtraArrayUnCorErrLogB_SBufExtraArrayUnCorErrData_127_64_LSB 0x0
#define QIB_7322_SBufExtraArrayUnCorErrLogB_SBufExtraArrayUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_SBufExtraArrayUnCorErrLogB_SBufExtraArrayUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_SBufExtraArrayUnCorErrLogC_OFFS 0x8A8
#define QIB_7322_SBufExtraArrayUnCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrAdd_3_0_LSB 0x3C
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrAdd_3_0_MSB 0x3F
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrAdd_3_0_RMASK 0xF
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrAddr_14_0_LSB 0x1C
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrAddr_14_0_MSB 0x2A
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrAddr_14_0_RMASK 0x7FFF
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_SBufExtraArrayUnCorErrLogC_SBufExtraArrayUnCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_SendPbcArrayUnCorErrLog_OFFS 0x8B0
#define QIB_7322_SendPbcArrayUnCorErrLog_DEF 0x0000000000000000
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrAddr_9_0_LSB 0x1D
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrAddr_9_0_MSB 0x26
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrAddr_9_0_RMASK 0x3FF
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrCheckBit_6_0_LSB 0x16
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrCheckBit_6_0_MSB 0x1C
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrCheckBit_6_0_RMASK 0x7F
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrData_21_0_LSB 0x0
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrData_21_0_MSB 0x15
#define QIB_7322_SendPbcArrayUnCorErrLog_SendPbcArrayUnCorErrData_21_0_RMASK 0x3FFFFF

#define QIB_7322_SBufVL15ArrayUnCorErrLogA_OFFS 0x8C0
#define QIB_7322_SBufVL15ArrayUnCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_SBufVL15ArrayUnCorErrLogA_SBufVL15ArrayUnCorErrData_63_0_LSB 0x0
#define QIB_7322_SBufVL15ArrayUnCorErrLogA_SBufVL15ArrayUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_SBufVL15ArrayUnCorErrLogA_SBufVL15ArrayUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_PcieCplDataBufrCorErrLogA_OFFS 0x900
#define QIB_7322_PcieCplDataBufrCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PcieCplDataBufrCorErrLogA_PcieCplDataBufrCorErrData_63_0_LSB 0x0
#define QIB_7322_PcieCplDataBufrCorErrLogA_PcieCplDataBufrCorErrData_63_0_MSB 0x3F
#define QIB_7322_PcieCplDataBufrCorErrLogA_PcieCplDataBufrCorErrData_63_0_RMASK 0x0

#define QIB_7322_PcieCplDataBufrCorErrLogB_OFFS 0x908
#define QIB_7322_PcieCplDataBufrCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PcieCplDataBufrCorErrLogB_PcieCplDataBufrCorErrData_127_64_LSB 0x0
#define QIB_7322_PcieCplDataBufrCorErrLogB_PcieCplDataBufrCorErrData_127_64_MSB 0x3F
#define QIB_7322_PcieCplDataBufrCorErrLogB_PcieCplDataBufrCorErrData_127_64_RMASK 0x0

#define QIB_7322_PcieCplDataBufrCorErrLogC_OFFS 0x910
#define QIB_7322_PcieCplDataBufrCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrAddr_13_0_LSB 0x1F
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrAddr_13_0_MSB 0x2C
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrCheckBit_21_0_LSB 0x9
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrCheckBit_21_0_MSB 0x1E
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrCheckBit_21_0_RMASK 0x3FFFFF
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrData_136_128_LSB 0x0
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrData_136_128_MSB 0x8
#define QIB_7322_PcieCplDataBufrCorErrLogC_PcieCplDataBufrCorErrData_136_128_RMASK 0x1FF

#define QIB_7322_PcieCplHdrBufrCorErrLogA_OFFS 0x920
#define QIB_7322_PcieCplHdrBufrCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PcieCplHdrBufrCorErrLogA_PcieCplHdrBufrCorErrHdr_63_0_LSB 0x0
#define QIB_7322_PcieCplHdrBufrCorErrLogA_PcieCplHdrBufrCorErrHdr_63_0_MSB 0x3F
#define QIB_7322_PcieCplHdrBufrCorErrLogA_PcieCplHdrBufrCorErrHdr_63_0_RMASK 0x0

#define QIB_7322_PcieCplHdrBufrCorErrLogB_OFFS 0x928
#define QIB_7322_PcieCplHdrBufrCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PcieCplHdrBufrCorErrLogB_PcieCplHdrBufrCorErrHdr_103_64_LSB 0x0
#define QIB_7322_PcieCplHdrBufrCorErrLogB_PcieCplHdrBufrCorErrHdr_103_64_MSB 0x27
#define QIB_7322_PcieCplHdrBufrCorErrLogB_PcieCplHdrBufrCorErrHdr_103_64_RMASK 0xFFFFFFFFFF

#define QIB_7322_PcieCplHdrBufrCorErrLogC_OFFS 0x930
#define QIB_7322_PcieCplHdrBufrCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PcieCplHdrBufrCorErrLogC_PcieCplHdrBufrCorErrAddr_8_0_LSB 0x10
#define QIB_7322_PcieCplHdrBufrCorErrLogC_PcieCplHdrBufrCorErrAddr_8_0_MSB 0x18
#define QIB_7322_PcieCplHdrBufrCorErrLogC_PcieCplHdrBufrCorErrAddr_8_0_RMASK 0x1FF
#define QIB_7322_PcieCplHdrBufrCorErrLogC_PcieCplHdrBufrCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_PcieCplHdrBufrCorErrLogC_PcieCplHdrBufrCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_PcieCplHdrBufrCorErrLogC_PcieCplHdrBufrCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_PciePDataBufrCorErrLogA_OFFS 0x940
#define QIB_7322_PciePDataBufrCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PciePDataBufrCorErrLogA_PciePDataBufrCorErrData_63_0_LSB 0x0
#define QIB_7322_PciePDataBufrCorErrLogA_PciePDataBufrCorErrData_63_0_MSB 0x3F
#define QIB_7322_PciePDataBufrCorErrLogA_PciePDataBufrCorErrData_63_0_RMASK 0x0

#define QIB_7322_PciePDataBufrCorErrLogB_OFFS 0x948
#define QIB_7322_PciePDataBufrCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PciePDataBufrCorErrLogB_PciePDataBufrCorErrData_127_64_LSB 0x0
#define QIB_7322_PciePDataBufrCorErrLogB_PciePDataBufrCorErrData_127_64_MSB 0x3F
#define QIB_7322_PciePDataBufrCorErrLogB_PciePDataBufrCorErrData_127_64_RMASK 0x0

#define QIB_7322_PciePDataBufrCorErrLogC_OFFS 0x950
#define QIB_7322_PciePDataBufrCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrAddr_13_0_LSB 0x1F
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrAddr_13_0_MSB 0x2C
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrCheckBit_21_0_LSB 0x9
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrCheckBit_21_0_MSB 0x1E
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrCheckBit_21_0_RMASK 0x3FFFFF
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrData_136_128_LSB 0x0
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrData_136_128_MSB 0x8
#define QIB_7322_PciePDataBufrCorErrLogC_PciePDataBufrCorErrData_136_128_RMASK 0x1FF

#define QIB_7322_PciePHdrBufrCorErrLogA_OFFS 0x960
#define QIB_7322_PciePHdrBufrCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PciePHdrBufrCorErrLogA_PciePHdrBufrCorErrData_63_0_LSB 0x0
#define QIB_7322_PciePHdrBufrCorErrLogA_PciePHdrBufrCorErrData_63_0_MSB 0x3F
#define QIB_7322_PciePHdrBufrCorErrLogA_PciePHdrBufrCorErrData_63_0_RMASK 0x0

#define QIB_7322_PciePHdrBufrCorErrLogB_OFFS 0x968
#define QIB_7322_PciePHdrBufrCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PciePHdrBufrCorErrLogB_PciePHdrBufrCorErrData_107_64_LSB 0x0
#define QIB_7322_PciePHdrBufrCorErrLogB_PciePHdrBufrCorErrData_107_64_MSB 0x2B
#define QIB_7322_PciePHdrBufrCorErrLogB_PciePHdrBufrCorErrData_107_64_RMASK 0xFFFFFFFFFFF

#define QIB_7322_PciePHdrBufrCorErrLogC_OFFS 0x970
#define QIB_7322_PciePHdrBufrCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PciePHdrBufrCorErrLogC_PciePHdrBufrCorErrAddr_8_0_LSB 0x10
#define QIB_7322_PciePHdrBufrCorErrLogC_PciePHdrBufrCorErrAddr_8_0_MSB 0x18
#define QIB_7322_PciePHdrBufrCorErrLogC_PciePHdrBufrCorErrAddr_8_0_RMASK 0x1FF
#define QIB_7322_PciePHdrBufrCorErrLogC_PciePHdrBufrCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_PciePHdrBufrCorErrLogC_PciePHdrBufrCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_PciePHdrBufrCorErrLogC_PciePHdrBufrCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_PcieRetryBufrCorErrLogA_OFFS 0x980
#define QIB_7322_PcieRetryBufrCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_PcieRetryBufrCorErrLogA_PcieRetryBufrCorErrData_63_0_LSB 0x0
#define QIB_7322_PcieRetryBufrCorErrLogA_PcieRetryBufrCorErrData_63_0_MSB 0x3F
#define QIB_7322_PcieRetryBufrCorErrLogA_PcieRetryBufrCorErrData_63_0_RMASK 0x0

#define QIB_7322_PcieRetryBufrCorErrLogB_OFFS 0x988
#define QIB_7322_PcieRetryBufrCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_PcieRetryBufrCorErrLogB_PcieRetryBufrCorErrData_127_64_LSB 0x0
#define QIB_7322_PcieRetryBufrCorErrLogB_PcieRetryBufrCorErrData_127_64_MSB 0x3F
#define QIB_7322_PcieRetryBufrCorErrLogB_PcieRetryBufrCorErrData_127_64_RMASK 0x0

#define QIB_7322_PcieRetryBufrCorErrLogC_OFFS 0x990
#define QIB_7322_PcieRetryBufrCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrAddr_13_0_LSB 0x1B
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrAddr_13_0_MSB 0x28
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrCheckBit_20_0_LSB 0x6
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrCheckBit_20_0_MSB 0x1A
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrCheckBit_20_0_RMASK 0x1FFFFF
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrData_133_128_LSB 0x0
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrData_133_128_MSB 0x5
#define QIB_7322_PcieRetryBufrCorErrLogC_PcieRetryBufrCorErrData_133_128_RMASK 0x3F

#define QIB_7322_RxTIDArrayCorErrLogA_OFFS 0xA00
#define QIB_7322_RxTIDArrayCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_RxTIDArrayCorErrLogA_RxTIDArrayCorErrCheckBit_11_0_LSB 0x28
#define QIB_7322_RxTIDArrayCorErrLogA_RxTIDArrayCorErrCheckBit_11_0_MSB 0x33
#define QIB_7322_RxTIDArrayCorErrLogA_RxTIDArrayCorErrCheckBit_11_0_RMASK 0xFFF
#define QIB_7322_RxTIDArrayCorErrLogA_RxTIDArrayCorErrData_39_0_LSB 0x0
#define QIB_7322_RxTIDArrayCorErrLogA_RxTIDArrayCorErrData_39_0_MSB 0x27
#define QIB_7322_RxTIDArrayCorErrLogA_RxTIDArrayCorErrData_39_0_RMASK 0xFFFFFFFFFF

#define QIB_7322_RxTIDArrayCorErrLogB_OFFS 0xA08
#define QIB_7322_RxTIDArrayCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_RxTIDArrayCorErrLogB_RxTIDArrayCorErrAddr_16_0_LSB 0x0
#define QIB_7322_RxTIDArrayCorErrLogB_RxTIDArrayCorErrAddr_16_0_MSB 0x10
#define QIB_7322_RxTIDArrayCorErrLogB_RxTIDArrayCorErrAddr_16_0_RMASK 0x1FFFF

#define QIB_7322_RxEagerArrayCorErrLogA_OFFS 0xA10
#define QIB_7322_RxEagerArrayCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_RxEagerArrayCorErrLogA_RxEagerArrayCorErrCheckBit_11_0_LSB 0x28
#define QIB_7322_RxEagerArrayCorErrLogA_RxEagerArrayCorErrCheckBit_11_0_MSB 0x33
#define QIB_7322_RxEagerArrayCorErrLogA_RxEagerArrayCorErrCheckBit_11_0_RMASK 0xFFF
#define QIB_7322_RxEagerArrayCorErrLogA_RxEagerArrayCorErrData_39_0_LSB 0x0
#define QIB_7322_RxEagerArrayCorErrLogA_RxEagerArrayCorErrData_39_0_MSB 0x27
#define QIB_7322_RxEagerArrayCorErrLogA_RxEagerArrayCorErrData_39_0_RMASK 0xFFFFFFFFFF

#define QIB_7322_RxEagerArrayCorErrLogB_OFFS 0xA18
#define QIB_7322_RxEagerArrayCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_RxEagerArrayCorErrLogB_RxEagerArrayCorErrAddr_17_0_LSB 0x0
#define QIB_7322_RxEagerArrayCorErrLogB_RxEagerArrayCorErrAddr_17_0_MSB 0x11
#define QIB_7322_RxEagerArrayCorErrLogB_RxEagerArrayCorErrAddr_17_0_RMASK 0x3FFFF

#define QIB_7322_SBufMainArrayCorErrLogA_OFFS 0xA80
#define QIB_7322_SBufMainArrayCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_SBufMainArrayCorErrLogA_SBufMainArrayCorErrData_63_0_LSB 0x0
#define QIB_7322_SBufMainArrayCorErrLogA_SBufMainArrayCorErrData_63_0_MSB 0x3F
#define QIB_7322_SBufMainArrayCorErrLogA_SBufMainArrayCorErrData_63_0_RMASK 0x0

#define QIB_7322_SBufMainArrayCorErrLogB_OFFS 0xA88
#define QIB_7322_SBufMainArrayCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_SBufMainArrayCorErrLogB_SBufMainArrayCorErrData_127_64_LSB 0x0
#define QIB_7322_SBufMainArrayCorErrLogB_SBufMainArrayCorErrData_127_64_MSB 0x3F
#define QIB_7322_SBufMainArrayCorErrLogB_SBufMainArrayCorErrData_127_64_RMASK 0x0

#define QIB_7322_SBufMainArrayCorErrLogC_OFFS 0xA90
#define QIB_7322_SBufMainArrayCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrDword_3_0_LSB 0x3C
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrDword_3_0_MSB 0x3F
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrDword_3_0_RMASK 0xF
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrAddr_18_0_LSB 0x1C
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrAddr_18_0_MSB 0x2E
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrAddr_18_0_RMASK 0x7FFFF
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_SBufMainArrayCorErrLogC_SBufMainArrayCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_SBufExtraArrayCorErrLogA_OFFS 0xA98
#define QIB_7322_SBufExtraArrayCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_SBufExtraArrayCorErrLogA_SBufExtraArrayCorErrData_63_0_LSB 0x0
#define QIB_7322_SBufExtraArrayCorErrLogA_SBufExtraArrayCorErrData_63_0_MSB 0x3F
#define QIB_7322_SBufExtraArrayCorErrLogA_SBufExtraArrayCorErrData_63_0_RMASK 0x0

#define QIB_7322_SBufExtraArrayCorErrLogB_OFFS 0xAA0
#define QIB_7322_SBufExtraArrayCorErrLogB_DEF 0x0000000000000000
#define QIB_7322_SBufExtraArrayCorErrLogB_SBufExtraArrayCorErrData_127_64_LSB 0x0
#define QIB_7322_SBufExtraArrayCorErrLogB_SBufExtraArrayCorErrData_127_64_MSB 0x3F
#define QIB_7322_SBufExtraArrayCorErrLogB_SBufExtraArrayCorErrData_127_64_RMASK 0x0

#define QIB_7322_SBufExtraArrayCorErrLogC_OFFS 0xAA8
#define QIB_7322_SBufExtraArrayCorErrLogC_DEF 0x0000000000000000
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrAdd_3_0_LSB 0x3C
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrAdd_3_0_MSB 0x3F
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrAdd_3_0_RMASK 0xF
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrAddr_14_0_LSB 0x1C
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrAddr_14_0_MSB 0x2A
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrAddr_14_0_RMASK 0x7FFF
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_SBufExtraArrayCorErrLogC_SBufExtraArrayCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_SendPbcArrayCorErrLog_OFFS 0xAB0
#define QIB_7322_SendPbcArrayCorErrLog_DEF 0x0000000000000000
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrAddr_9_0_LSB 0x1D
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrAddr_9_0_MSB 0x26
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrAddr_9_0_RMASK 0x3FF
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrCheckBit_6_0_LSB 0x16
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrCheckBit_6_0_MSB 0x1C
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrCheckBit_6_0_RMASK 0x7F
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrData_21_0_LSB 0x0
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrData_21_0_MSB 0x15
#define QIB_7322_SendPbcArrayCorErrLog_SendPbcArrayCorErrData_21_0_RMASK 0x3FFFFF

#define QIB_7322_SBufVL15ArrayCorErrLogA_OFFS 0xAC0
#define QIB_7322_SBufVL15ArrayCorErrLogA_DEF 0x0000000000000000
#define QIB_7322_SBufVL15ArrayCorErrLogA_SBufVL15ArrayCorErrData_63_0_LSB 0x0
#define QIB_7322_SBufVL15ArrayCorErrLogA_SBufVL15ArrayCorErrData_63_0_MSB 0x3F
#define QIB_7322_SBufVL15ArrayCorErrLogA_SBufVL15ArrayCorErrData_63_0_RMASK 0x0

#define QIB_7322_RcvAvailTimeOut0_OFFS 0xC00
#define QIB_7322_RcvAvailTimeOut0_DEF 0x0000000000000000
#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_LSB 0x10
#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_MSB 0x1F
#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_RMASK 0xFFFF
#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_LSB 0x0
#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_MSB 0xF
#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_RMASK 0xFFFF

#define QIB_7322_CntrRegBase_0_OFFS 0x1028
#define QIB_7322_CntrRegBase_0_DEF 0x0000000000012000

#define QIB_7322_ErrMask_0_OFFS 0x1080
#define QIB_7322_ErrMask_0_DEF 0x0000000000000000
#define QIB_7322_ErrMask_0_IBStatusChangedMask_LSB 0x3A
#define QIB_7322_ErrMask_0_IBStatusChangedMask_MSB 0x3A
#define QIB_7322_ErrMask_0_IBStatusChangedMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SHeadersErrMask_LSB 0x39
#define QIB_7322_ErrMask_0_SHeadersErrMask_MSB 0x39
#define QIB_7322_ErrMask_0_SHeadersErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_LSB 0x36
#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_MSB 0x36
#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaHaltErrMask_LSB 0x31
#define QIB_7322_ErrMask_0_SDmaHaltErrMask_MSB 0x31
#define QIB_7322_ErrMask_0_SDmaHaltErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_LSB 0x30
#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_MSB 0x30
#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_LSB 0x2F
#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_MSB 0x2F
#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_LSB 0x2E
#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_MSB 0x2E
#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_LSB 0x2D
#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_MSB 0x2D
#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_LSB 0x2C
#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_MSB 0x2C
#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDma1stDescErrMask_LSB 0x2B
#define QIB_7322_ErrMask_0_SDma1stDescErrMask_MSB 0x2B
#define QIB_7322_ErrMask_0_SDma1stDescErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaBaseErrMask_LSB 0x2A
#define QIB_7322_ErrMask_0_SDmaBaseErrMask_MSB 0x2A
#define QIB_7322_ErrMask_0_SDmaBaseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_LSB 0x29
#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_MSB 0x29
#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_LSB 0x28
#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_MSB 0x28
#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_LSB 0x27
#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_MSB 0x27
#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_LSB 0x26
#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_MSB 0x26
#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_LSB 0x25
#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_MSB 0x25
#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_LSB 0x24
#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_MSB 0x24
#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_LSB 0x22
#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_MSB 0x22
#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_LSB 0x21
#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_MSB 0x21
#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendPktLenErrMask_LSB 0x20
#define QIB_7322_ErrMask_0_SendPktLenErrMask_MSB 0x20
#define QIB_7322_ErrMask_0_SendPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendUnderRunErrMask_LSB 0x1F
#define QIB_7322_ErrMask_0_SendUnderRunErrMask_MSB 0x1F
#define QIB_7322_ErrMask_0_SendUnderRunErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_LSB 0x1E
#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_MSB 0x1E
#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_LSB 0x1D
#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_MSB 0x1D
#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_LSB 0x11
#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_MSB 0x11
#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvHdrErrMask_LSB 0x10
#define QIB_7322_ErrMask_0_RcvHdrErrMask_MSB 0x10
#define QIB_7322_ErrMask_0_RcvHdrErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_LSB 0xF
#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_MSB 0xF
#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvBadTidErrMask_LSB 0xE
#define QIB_7322_ErrMask_0_RcvBadTidErrMask_MSB 0xE
#define QIB_7322_ErrMask_0_RcvBadTidErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_LSB 0xB
#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_MSB 0xB
#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_LSB 0xA
#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_MSB 0xA
#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvEBPErrMask_LSB 0x9
#define QIB_7322_ErrMask_0_RcvEBPErrMask_MSB 0x9
#define QIB_7322_ErrMask_0_RcvEBPErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_LSB 0x8
#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_MSB 0x8
#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_LSB 0x7
#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_MSB 0x7
#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_LSB 0x6
#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_MSB 0x6
#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_LSB 0x5
#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_MSB 0x5
#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_LSB 0x4
#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_MSB 0x4
#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_LSB 0x3
#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_MSB 0x3
#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvICRCErrMask_LSB 0x2
#define QIB_7322_ErrMask_0_RcvICRCErrMask_MSB 0x2
#define QIB_7322_ErrMask_0_RcvICRCErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvVCRCErrMask_LSB 0x1
#define QIB_7322_ErrMask_0_RcvVCRCErrMask_MSB 0x1
#define QIB_7322_ErrMask_0_RcvVCRCErrMask_RMASK 0x1
#define QIB_7322_ErrMask_0_RcvFormatErrMask_LSB 0x0
#define QIB_7322_ErrMask_0_RcvFormatErrMask_MSB 0x0
#define QIB_7322_ErrMask_0_RcvFormatErrMask_RMASK 0x1

#define QIB_7322_ErrStatus_0_OFFS 0x1088
#define QIB_7322_ErrStatus_0_DEF 0x0000000000000000
#define QIB_7322_ErrStatus_0_IBStatusChanged_LSB 0x3A
#define QIB_7322_ErrStatus_0_IBStatusChanged_MSB 0x3A
#define QIB_7322_ErrStatus_0_IBStatusChanged_RMASK 0x1
#define QIB_7322_ErrStatus_0_SHeadersErr_LSB 0x39
#define QIB_7322_ErrStatus_0_SHeadersErr_MSB 0x39
#define QIB_7322_ErrStatus_0_SHeadersErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_LSB 0x36
#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_MSB 0x36
#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaHaltErr_LSB 0x31
#define QIB_7322_ErrStatus_0_SDmaHaltErr_MSB 0x31
#define QIB_7322_ErrStatus_0_SDmaHaltErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_LSB 0x30
#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_MSB 0x30
#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_LSB 0x2F
#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_MSB 0x2F
#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_LSB 0x2E
#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_MSB 0x2E
#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaDwEnErr_LSB 0x2D
#define QIB_7322_ErrStatus_0_SDmaDwEnErr_MSB 0x2D
#define QIB_7322_ErrStatus_0_SDmaDwEnErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_LSB 0x2C
#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_MSB 0x2C
#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDma1stDescErr_LSB 0x2B
#define QIB_7322_ErrStatus_0_SDma1stDescErr_MSB 0x2B
#define QIB_7322_ErrStatus_0_SDma1stDescErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaBaseErr_LSB 0x2A
#define QIB_7322_ErrStatus_0_SDmaBaseErr_MSB 0x2A
#define QIB_7322_ErrStatus_0_SDmaBaseErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_LSB 0x29
#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_MSB 0x29
#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_LSB 0x28
#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_MSB 0x28
#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_LSB 0x27
#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_MSB 0x27
#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendBufMisuseErr_LSB 0x26
#define QIB_7322_ErrStatus_0_SendBufMisuseErr_MSB 0x26
#define QIB_7322_ErrStatus_0_SendBufMisuseErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_LSB 0x25
#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_MSB 0x25
#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_LSB 0x24
#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_MSB 0x24
#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_LSB 0x22
#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_MSB 0x22
#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_LSB 0x21
#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_MSB 0x21
#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendPktLenErr_LSB 0x20
#define QIB_7322_ErrStatus_0_SendPktLenErr_MSB 0x20
#define QIB_7322_ErrStatus_0_SendPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendUnderRunErr_LSB 0x1F
#define QIB_7322_ErrStatus_0_SendUnderRunErr_MSB 0x1F
#define QIB_7322_ErrStatus_0_SendUnderRunErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_LSB 0x1E
#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_MSB 0x1E
#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_SendMinPktLenErr_LSB 0x1D
#define QIB_7322_ErrStatus_0_SendMinPktLenErr_MSB 0x1D
#define QIB_7322_ErrStatus_0_SendMinPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_LSB 0x11
#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_MSB 0x11
#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvHdrErr_LSB 0x10
#define QIB_7322_ErrStatus_0_RcvHdrErr_MSB 0x10
#define QIB_7322_ErrStatus_0_RcvHdrErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvHdrLenErr_LSB 0xF
#define QIB_7322_ErrStatus_0_RcvHdrLenErr_MSB 0xF
#define QIB_7322_ErrStatus_0_RcvHdrLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvBadTidErr_LSB 0xE
#define QIB_7322_ErrStatus_0_RcvBadTidErr_MSB 0xE
#define QIB_7322_ErrStatus_0_RcvBadTidErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvBadVersionErr_LSB 0xB
#define QIB_7322_ErrStatus_0_RcvBadVersionErr_MSB 0xB
#define QIB_7322_ErrStatus_0_RcvBadVersionErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvIBFlowErr_LSB 0xA
#define QIB_7322_ErrStatus_0_RcvIBFlowErr_MSB 0xA
#define QIB_7322_ErrStatus_0_RcvIBFlowErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvEBPErr_LSB 0x9
#define QIB_7322_ErrStatus_0_RcvEBPErr_MSB 0x9
#define QIB_7322_ErrStatus_0_RcvEBPErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_LSB 0x8
#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_MSB 0x8
#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_LSB 0x7
#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_MSB 0x7
#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_LSB 0x6
#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_MSB 0x6
#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_LSB 0x5
#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_MSB 0x5
#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_LSB 0x4
#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_MSB 0x4
#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_LSB 0x3
#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_MSB 0x3
#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvICRCErr_LSB 0x2
#define QIB_7322_ErrStatus_0_RcvICRCErr_MSB 0x2
#define QIB_7322_ErrStatus_0_RcvICRCErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvVCRCErr_LSB 0x1
#define QIB_7322_ErrStatus_0_RcvVCRCErr_MSB 0x1
#define QIB_7322_ErrStatus_0_RcvVCRCErr_RMASK 0x1
#define QIB_7322_ErrStatus_0_RcvFormatErr_LSB 0x0
#define QIB_7322_ErrStatus_0_RcvFormatErr_MSB 0x0
#define QIB_7322_ErrStatus_0_RcvFormatErr_RMASK 0x1

#define QIB_7322_ErrClear_0_OFFS 0x1090
#define QIB_7322_ErrClear_0_DEF 0x0000000000000000
#define QIB_7322_ErrClear_0_IBStatusChangedClear_LSB 0x3A
#define QIB_7322_ErrClear_0_IBStatusChangedClear_MSB 0x3A
#define QIB_7322_ErrClear_0_IBStatusChangedClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SHeadersErrClear_LSB 0x39
#define QIB_7322_ErrClear_0_SHeadersErrClear_MSB 0x39
#define QIB_7322_ErrClear_0_SHeadersErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_LSB 0x36
#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_MSB 0x36
#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaHaltErrClear_LSB 0x31
#define QIB_7322_ErrClear_0_SDmaHaltErrClear_MSB 0x31
#define QIB_7322_ErrClear_0_SDmaHaltErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_LSB 0x30
#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_MSB 0x30
#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_LSB 0x2F
#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_MSB 0x2F
#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_LSB 0x2E
#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_MSB 0x2E
#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_LSB 0x2D
#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_MSB 0x2D
#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_LSB 0x2C
#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_MSB 0x2C
#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDma1stDescErrClear_LSB 0x2B
#define QIB_7322_ErrClear_0_SDma1stDescErrClear_MSB 0x2B
#define QIB_7322_ErrClear_0_SDma1stDescErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaBaseErrClear_LSB 0x2A
#define QIB_7322_ErrClear_0_SDmaBaseErrClear_MSB 0x2A
#define QIB_7322_ErrClear_0_SDmaBaseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_LSB 0x29
#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_MSB 0x29
#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_LSB 0x28
#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_MSB 0x28
#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_LSB 0x27
#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_MSB 0x27
#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_LSB 0x26
#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_MSB 0x26
#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_LSB 0x25
#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_MSB 0x25
#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_LSB 0x24
#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_MSB 0x24
#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_LSB 0x22
#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_MSB 0x22
#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_LSB 0x21
#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_MSB 0x21
#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendPktLenErrClear_LSB 0x20
#define QIB_7322_ErrClear_0_SendPktLenErrClear_MSB 0x20
#define QIB_7322_ErrClear_0_SendPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendUnderRunErrClear_LSB 0x1F
#define QIB_7322_ErrClear_0_SendUnderRunErrClear_MSB 0x1F
#define QIB_7322_ErrClear_0_SendUnderRunErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_LSB 0x1E
#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_MSB 0x1E
#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_LSB 0x1D
#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_MSB 0x1D
#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_LSB 0x11
#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_MSB 0x11
#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvHdrErrClear_LSB 0x10
#define QIB_7322_ErrClear_0_RcvHdrErrClear_MSB 0x10
#define QIB_7322_ErrClear_0_RcvHdrErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_LSB 0xF
#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_MSB 0xF
#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvBadTidErrClear_LSB 0xE
#define QIB_7322_ErrClear_0_RcvBadTidErrClear_MSB 0xE
#define QIB_7322_ErrClear_0_RcvBadTidErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_LSB 0xB
#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_MSB 0xB
#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_LSB 0xA
#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_MSB 0xA
#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvEBPErrClear_LSB 0x9
#define QIB_7322_ErrClear_0_RcvEBPErrClear_MSB 0x9
#define QIB_7322_ErrClear_0_RcvEBPErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_LSB 0x8
#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_MSB 0x8
#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_LSB 0x7
#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_MSB 0x7
#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_LSB 0x6
#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_MSB 0x6
#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_LSB 0x5
#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_MSB 0x5
#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_LSB 0x4
#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_MSB 0x4
#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_LSB 0x3
#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_MSB 0x3
#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvICRCErrClear_LSB 0x2
#define QIB_7322_ErrClear_0_RcvICRCErrClear_MSB 0x2
#define QIB_7322_ErrClear_0_RcvICRCErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvVCRCErrClear_LSB 0x1
#define QIB_7322_ErrClear_0_RcvVCRCErrClear_MSB 0x1
#define QIB_7322_ErrClear_0_RcvVCRCErrClear_RMASK 0x1
#define QIB_7322_ErrClear_0_RcvFormatErrClear_LSB 0x0
#define QIB_7322_ErrClear_0_RcvFormatErrClear_MSB 0x0
#define QIB_7322_ErrClear_0_RcvFormatErrClear_RMASK 0x1

#define QIB_7322_TXEStatus_0_OFFS 0x10B8
#define QIB_7322_TXEStatus_0_DEF 0x0000000XC00080FF
#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_LSB 0x1F
#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_MSB 0x1F
#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_RMASK 0x1
#define QIB_7322_TXEStatus_0_RmFifoEmpty_LSB 0x1E
#define QIB_7322_TXEStatus_0_RmFifoEmpty_MSB 0x1E
#define QIB_7322_TXEStatus_0_RmFifoEmpty_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_LSB 0xF
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_MSB 0xF
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_LSB 0x7
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_MSB 0x7
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_LSB 0x6
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_MSB 0x6
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_LSB 0x5
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_MSB 0x5
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_LSB 0x4
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_MSB 0x4
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_LSB 0x3
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_MSB 0x3
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_LSB 0x2
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_MSB 0x2
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_LSB 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_MSB 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_RMASK 0x1
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_LSB 0x0
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_MSB 0x0
#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_RMASK 0x1

#define QIB_7322_RcvCtrl_0_OFFS 0x1100
#define QIB_7322_RcvCtrl_0_DEF 0x0000000000000000
#define QIB_7322_RcvCtrl_0_RcvResetCredit_LSB 0x2A
#define QIB_7322_RcvCtrl_0_RcvResetCredit_MSB 0x2A
#define QIB_7322_RcvCtrl_0_RcvResetCredit_RMASK 0x1
#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_LSB 0x29
#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_MSB 0x29
#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_RMASK 0x1
#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_LSB 0x28
#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_MSB 0x28
#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_RMASK 0x1
#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_LSB 0x27
#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_MSB 0x27
#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_RMASK 0x1
#define QIB_7322_RcvCtrl_0_ContextEnableUser_LSB 0x2
#define QIB_7322_RcvCtrl_0_ContextEnableUser_MSB 0x11
#define QIB_7322_RcvCtrl_0_ContextEnableUser_RMASK 0xFFFF
#define QIB_7322_RcvCtrl_0_ContextEnableKernel_LSB 0x0
#define QIB_7322_RcvCtrl_0_ContextEnableKernel_MSB 0x0
#define QIB_7322_RcvCtrl_0_ContextEnableKernel_RMASK 0x1

#define QIB_7322_RcvBTHQP_0_OFFS 0x1108
#define QIB_7322_RcvBTHQP_0_DEF 0x0000000000000000
#define QIB_7322_RcvBTHQP_0_RcvBTHQP_LSB 0x0
#define QIB_7322_RcvBTHQP_0_RcvBTHQP_MSB 0x17
#define QIB_7322_RcvBTHQP_0_RcvBTHQP_RMASK 0xFFFFFF

#define QIB_7322_RcvQPMapTableA_0_OFFS 0x1110
#define QIB_7322_RcvQPMapTableA_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_LSB 0x19
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_MSB 0x1D
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_LSB 0x14
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_MSB 0x18
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_LSB 0xF
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_MSB 0x13
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_LSB 0xA
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_MSB 0xE
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_LSB 0x5
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_MSB 0x9
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_LSB 0x0
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_MSB 0x4
#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_RMASK 0x1F

#define QIB_7322_RcvQPMapTableB_0_OFFS 0x1118
#define QIB_7322_RcvQPMapTableB_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_LSB 0x19
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_MSB 0x1D
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_LSB 0x14
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_MSB 0x18
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_LSB 0xF
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_MSB 0x13
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_LSB 0xA
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_MSB 0xE
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_LSB 0x5
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_MSB 0x9
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_LSB 0x0
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_MSB 0x4
#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_RMASK 0x1F

#define QIB_7322_RcvQPMapTableC_0_OFFS 0x1120
#define QIB_7322_RcvQPMapTableC_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_LSB 0x19
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_MSB 0x1D
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_LSB 0x14
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_MSB 0x18
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_LSB 0xF
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_MSB 0x13
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_LSB 0xA
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_MSB 0xE
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_LSB 0x5
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_MSB 0x9
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_LSB 0x0
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_MSB 0x4
#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_RMASK 0x1F

#define QIB_7322_RcvQPMapTableD_0_OFFS 0x1128
#define QIB_7322_RcvQPMapTableD_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_LSB 0x19
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_MSB 0x1D
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_LSB 0x14
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_MSB 0x18
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_LSB 0xF
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_MSB 0x13
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_LSB 0xA
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_MSB 0xE
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_LSB 0x5
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_MSB 0x9
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_LSB 0x0
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_MSB 0x4
#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_RMASK 0x1F

#define QIB_7322_RcvQPMapTableE_0_OFFS 0x1130
#define QIB_7322_RcvQPMapTableE_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_LSB 0x19
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_MSB 0x1D
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_LSB 0x14
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_MSB 0x18
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_LSB 0xF
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_MSB 0x13
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_LSB 0xA
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_MSB 0xE
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_LSB 0x5
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_MSB 0x9
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_LSB 0x0
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_MSB 0x4
#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_RMASK 0x1F

#define QIB_7322_RcvQPMapTableF_0_OFFS 0x1138
#define QIB_7322_RcvQPMapTableF_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_LSB 0x5
#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_MSB 0x9
#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_RMASK 0x1F
#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_LSB 0x0
#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_MSB 0x4
#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_RMASK 0x1F

#define QIB_7322_PSStat_0_OFFS 0x1140
#define QIB_7322_PSStat_0_DEF 0x0000000000000000

#define QIB_7322_PSStart_0_OFFS 0x1148
#define QIB_7322_PSStart_0_DEF 0x0000000000000000

#define QIB_7322_PSInterval_0_OFFS 0x1150
#define QIB_7322_PSInterval_0_DEF 0x0000000000000000

#define QIB_7322_RcvStatus_0_OFFS 0x1160
#define QIB_7322_RcvStatus_0_DEF 0x0000000000000000
#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_LSB 0x1
#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_MSB 0x5
#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_RMASK 0x1F
#define QIB_7322_RcvStatus_0_RxPktInProgress_LSB 0x0
#define QIB_7322_RcvStatus_0_RxPktInProgress_MSB 0x0
#define QIB_7322_RcvStatus_0_RxPktInProgress_RMASK 0x1

#define QIB_7322_RcvPartitionKey_0_OFFS 0x1168
#define QIB_7322_RcvPartitionKey_0_DEF 0x0000000000000000

#define QIB_7322_RcvQPMulticastContext_0_OFFS 0x1170
#define QIB_7322_RcvQPMulticastContext_0_DEF 0x0000000000000000
#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_LSB 0x0
#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_MSB 0x4
#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_RMASK 0x1F

#define QIB_7322_RcvPktLEDCnt_0_OFFS 0x1178
#define QIB_7322_RcvPktLEDCnt_0_DEF 0x0000000000000000
#define QIB_7322_RcvPktLEDCnt_0_ONperiod_LSB 0x20
#define QIB_7322_RcvPktLEDCnt_0_ONperiod_MSB 0x3F
#define QIB_7322_RcvPktLEDCnt_0_ONperiod_RMASK 0xFFFFFFFF
#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_LSB 0x0
#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_MSB 0x1F
#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_RMASK 0xFFFFFFFF

#define QIB_7322_SendDmaIdleCnt_0_OFFS 0x1180
#define QIB_7322_SendDmaIdleCnt_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_LSB 0x0
#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_MSB 0xF
#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_RMASK 0xFFFF

#define QIB_7322_SendDmaReloadCnt_0_OFFS 0x1188
#define QIB_7322_SendDmaReloadCnt_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_LSB 0x0
#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_MSB 0xF
#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_RMASK 0xFFFF

#define QIB_7322_SendDmaDescCnt_0_OFFS 0x1190
#define QIB_7322_SendDmaDescCnt_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_LSB 0x0
#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_MSB 0xF
#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_RMASK 0xFFFF

#define QIB_7322_SendCtrl_0_OFFS 0x11C0
#define QIB_7322_SendCtrl_0_DEF 0x0000000000000000
#define QIB_7322_SendCtrl_0_IBVLArbiterEn_LSB 0xF
#define QIB_7322_SendCtrl_0_IBVLArbiterEn_MSB 0xF
#define QIB_7322_SendCtrl_0_IBVLArbiterEn_RMASK 0x1
#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_LSB 0xE
#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_MSB 0xE
#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_RMASK 0x1
#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_LSB 0xD
#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_MSB 0xD
#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_RMASK 0x1
#define QIB_7322_SendCtrl_0_SDmaHalt_LSB 0xC
#define QIB_7322_SendCtrl_0_SDmaHalt_MSB 0xC
#define QIB_7322_SendCtrl_0_SDmaHalt_RMASK 0x1
#define QIB_7322_SendCtrl_0_SDmaEnable_LSB 0xB
#define QIB_7322_SendCtrl_0_SDmaEnable_MSB 0xB
#define QIB_7322_SendCtrl_0_SDmaEnable_RMASK 0x1
#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_LSB 0xA
#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_MSB 0xA
#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_RMASK 0x1
#define QIB_7322_SendCtrl_0_SDmaIntEnable_LSB 0x9
#define QIB_7322_SendCtrl_0_SDmaIntEnable_MSB 0x9
#define QIB_7322_SendCtrl_0_SDmaIntEnable_RMASK 0x1
#define QIB_7322_SendCtrl_0_SDmaCleanup_LSB 0x8
#define QIB_7322_SendCtrl_0_SDmaCleanup_MSB 0x8
#define QIB_7322_SendCtrl_0_SDmaCleanup_RMASK 0x1
#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_LSB 0x7
#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_MSB 0x7
#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_RMASK 0x1
#define QIB_7322_SendCtrl_0_SendEnable_LSB 0x3
#define QIB_7322_SendCtrl_0_SendEnable_MSB 0x3
#define QIB_7322_SendCtrl_0_SendEnable_RMASK 0x1
#define QIB_7322_SendCtrl_0_TxeBypassIbc_LSB 0x1
#define QIB_7322_SendCtrl_0_TxeBypassIbc_MSB 0x1
#define QIB_7322_SendCtrl_0_TxeBypassIbc_RMASK 0x1
#define QIB_7322_SendCtrl_0_TxeAbortIbc_LSB 0x0
#define QIB_7322_SendCtrl_0_TxeAbortIbc_MSB 0x0
#define QIB_7322_SendCtrl_0_TxeAbortIbc_RMASK 0x1

#define QIB_7322_SendDmaBase_0_OFFS 0x11F8
#define QIB_7322_SendDmaBase_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaBase_0_SendDmaBase_LSB 0x0
#define QIB_7322_SendDmaBase_0_SendDmaBase_MSB 0x2F
#define QIB_7322_SendDmaBase_0_SendDmaBase_RMASK 0xFFFFFFFFFFFF

#define QIB_7322_SendDmaLenGen_0_OFFS 0x1200
#define QIB_7322_SendDmaLenGen_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaLenGen_0_Generation_LSB 0x10
#define QIB_7322_SendDmaLenGen_0_Generation_MSB 0x12
#define QIB_7322_SendDmaLenGen_0_Generation_RMASK 0x7
#define QIB_7322_SendDmaLenGen_0_Length_LSB 0x0
#define QIB_7322_SendDmaLenGen_0_Length_MSB 0xF
#define QIB_7322_SendDmaLenGen_0_Length_RMASK 0xFFFF

#define QIB_7322_SendDmaTail_0_OFFS 0x1208
#define QIB_7322_SendDmaTail_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaTail_0_SendDmaTail_LSB 0x0
#define QIB_7322_SendDmaTail_0_SendDmaTail_MSB 0xF
#define QIB_7322_SendDmaTail_0_SendDmaTail_RMASK 0xFFFF

#define QIB_7322_SendDmaHead_0_OFFS 0x1210
#define QIB_7322_SendDmaHead_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_LSB 0x20
#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_MSB 0x2F
#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_RMASK 0xFFFF
#define QIB_7322_SendDmaHead_0_SendDmaHead_LSB 0x0
#define QIB_7322_SendDmaHead_0_SendDmaHead_MSB 0xF
#define QIB_7322_SendDmaHead_0_SendDmaHead_RMASK 0xFFFF

#define QIB_7322_SendDmaHeadAddr_0_OFFS 0x1218
#define QIB_7322_SendDmaHeadAddr_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_LSB 0x0
#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_MSB 0x2F
#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF

#define QIB_7322_SendDmaBufMask0_0_OFFS 0x1220
#define QIB_7322_SendDmaBufMask0_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_LSB 0x0
#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_MSB 0x3F
#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_RMASK 0x0

#define QIB_7322_SendDmaStatus_0_OFFS 0x1238
#define QIB_7322_SendDmaStatus_0_DEF 0x0000000042000000
#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_LSB 0x3F
#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_MSB 0x3F
#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_HaltInProg_LSB 0x3E
#define QIB_7322_SendDmaStatus_0_HaltInProg_MSB 0x3E
#define QIB_7322_SendDmaStatus_0_HaltInProg_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_LSB 0x3D
#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_MSB 0x3D
#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_LSB 0x2F
#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_MSB 0x3C
#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_RMASK 0x3FFF
#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_LSB 0x28
#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_MSB 0x2E
#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_RMASK 0x7F
#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_LSB 0x20
#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_MSB 0x27
#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_RMASK 0xFF
#define QIB_7322_SendDmaStatus_0_ScbFull_LSB 0x1F
#define QIB_7322_SendDmaStatus_0_ScbFull_MSB 0x1F
#define QIB_7322_SendDmaStatus_0_ScbFull_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_ScbEmpty_LSB 0x1E
#define QIB_7322_SendDmaStatus_0_ScbEmpty_MSB 0x1E
#define QIB_7322_SendDmaStatus_0_ScbEmpty_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_ScbEntryValid_LSB 0x1D
#define QIB_7322_SendDmaStatus_0_ScbEntryValid_MSB 0x1D
#define QIB_7322_SendDmaStatus_0_ScbEntryValid_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_LSB 0x1C
#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_MSB 0x1C
#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_LSB 0x1B
#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_MSB 0x1B
#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_LSB 0x1A
#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_MSB 0x1A
#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_LSB 0x19
#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_MSB 0x19
#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_SplFifoFull_LSB 0x18
#define QIB_7322_SendDmaStatus_0_SplFifoFull_MSB 0x18
#define QIB_7322_SendDmaStatus_0_SplFifoFull_RMASK 0x1
#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_LSB 0x10
#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_MSB 0x17
#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_RMASK 0xFF
#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_LSB 0x0
#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_MSB 0xF
#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_RMASK 0xFFFF

#define QIB_7322_SendDmaPriorityThld_0_OFFS 0x1258
#define QIB_7322_SendDmaPriorityThld_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_LSB 0x0
#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_MSB 0x3
#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_RMASK 0xF

#define QIB_7322_SendHdrErrSymptom_0_OFFS 0x1260
#define QIB_7322_SendHdrErrSymptom_0_DEF 0x0000000000000000
#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_LSB 0x6
#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_MSB 0x6
#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_0_GRHFail_LSB 0x5
#define QIB_7322_SendHdrErrSymptom_0_GRHFail_MSB 0x5
#define QIB_7322_SendHdrErrSymptom_0_GRHFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_LSB 0x4
#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_MSB 0x4
#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_0_QPFail_LSB 0x3
#define QIB_7322_SendHdrErrSymptom_0_QPFail_MSB 0x3
#define QIB_7322_SendHdrErrSymptom_0_QPFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_LSB 0x2
#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_MSB 0x2
#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_LSB 0x1
#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_MSB 0x1
#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_LSB 0x0
#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_MSB 0x0
#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_RMASK 0x1

#define QIB_7322_RxCreditVL0_0_OFFS 0x1280
#define QIB_7322_RxCreditVL0_0_DEF 0x0000000000000000
#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_LSB 0x10
#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_MSB 0x1B
#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_RMASK 0xFFF
#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_LSB 0x0
#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_MSB 0xB
#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_RMASK 0xFFF

#define QIB_7322_SendDmaBufUsed0_0_OFFS 0x1480
#define QIB_7322_SendDmaBufUsed0_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_LSB 0x0
#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_MSB 0x3F
#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_RMASK 0x0

#define QIB_7322_SendDmaReqTagUsed_0_OFFS 0x1498
#define QIB_7322_SendDmaReqTagUsed_0_DEF 0x0000000000000000
#define QIB_7322_SendDmaReqTagUsed_0_ReqTagUsed_7_0_LSB 0x0
#define QIB_7322_SendDmaReqTagUsed_0_ReqTagUsed_7_0_MSB 0x7
#define QIB_7322_SendDmaReqTagUsed_0_ReqTagUsed_7_0_RMASK 0xFF

#define QIB_7322_SendCheckControl_0_OFFS 0x14A8
#define QIB_7322_SendCheckControl_0_DEF 0x0000000000000000
#define QIB_7322_SendCheckControl_0_PKey_En_LSB 0x4
#define QIB_7322_SendCheckControl_0_PKey_En_MSB 0x4
#define QIB_7322_SendCheckControl_0_PKey_En_RMASK 0x1
#define QIB_7322_SendCheckControl_0_BTHQP_En_LSB 0x3
#define QIB_7322_SendCheckControl_0_BTHQP_En_MSB 0x3
#define QIB_7322_SendCheckControl_0_BTHQP_En_RMASK 0x1
#define QIB_7322_SendCheckControl_0_SLID_En_LSB 0x2
#define QIB_7322_SendCheckControl_0_SLID_En_MSB 0x2
#define QIB_7322_SendCheckControl_0_SLID_En_RMASK 0x1
#define QIB_7322_SendCheckControl_0_RawIPV6_En_LSB 0x1
#define QIB_7322_SendCheckControl_0_RawIPV6_En_MSB 0x1
#define QIB_7322_SendCheckControl_0_RawIPV6_En_RMASK 0x1
#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_LSB 0x0
#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_MSB 0x0
#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_RMASK 0x1

#define QIB_7322_SendIBSLIDMask_0_OFFS 0x14B0
#define QIB_7322_SendIBSLIDMask_0_DEF 0x0000000000000000
#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_LSB 0x0
#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_MSB 0xF
#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 0xFFFF

#define QIB_7322_SendIBSLIDAssign_0_OFFS 0x14B8
#define QIB_7322_SendIBSLIDAssign_0_DEF 0x0000000000000000
#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_LSB 0x0
#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_MSB 0xF
#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 0xFFFF

#define QIB_7322_IBCStatusA_0_OFFS 0x1540
#define QIB_7322_IBCStatusA_0_DEF 0x0000000000000X02
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_LSB 0x27
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_MSB 0x27
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_LSB 0x26
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_MSB 0x26
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_LSB 0x25
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_MSB 0x25
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_LSB 0x24
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_MSB 0x24
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_LSB 0x23
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_MSB 0x23
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_LSB 0x22
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_MSB 0x22
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_LSB 0x21
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_MSB 0x21
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_LSB 0x20
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_MSB 0x20
#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_RMASK 0x1
#define QIB_7322_IBCStatusA_0_TxReady_LSB 0x1E
#define QIB_7322_IBCStatusA_0_TxReady_MSB 0x1E
#define QIB_7322_IBCStatusA_0_TxReady_RMASK 0x1
#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_LSB 0x1D
#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_MSB 0x1D
#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_RMASK 0x1
#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_LSB 0xF
#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_MSB 0xF
#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_RMASK 0x1
#define QIB_7322_IBCStatusA_0_ScrambleEn_LSB 0xE
#define QIB_7322_IBCStatusA_0_ScrambleEn_MSB 0xE
#define QIB_7322_IBCStatusA_0_ScrambleEn_RMASK 0x1
#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_LSB 0xD
#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_MSB 0xD
#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_RMASK 0x1
#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_LSB 0xC
#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_MSB 0xC
#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_RMASK 0x1
#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_LSB 0xA
#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_MSB 0xA
#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_RMASK 0x1
#define QIB_7322_IBCStatusA_0_LinkWidthActive_LSB 0x9
#define QIB_7322_IBCStatusA_0_LinkWidthActive_MSB 0x9
#define QIB_7322_IBCStatusA_0_LinkWidthActive_RMASK 0x1
#define QIB_7322_IBCStatusA_0_LinkSpeedActive_LSB 0x8
#define QIB_7322_IBCStatusA_0_LinkSpeedActive_MSB 0x8
#define QIB_7322_IBCStatusA_0_LinkSpeedActive_RMASK 0x1
#define QIB_7322_IBCStatusA_0_LinkState_LSB 0x5
#define QIB_7322_IBCStatusA_0_LinkState_MSB 0x7
#define QIB_7322_IBCStatusA_0_LinkState_RMASK 0x7
#define QIB_7322_IBCStatusA_0_LinkTrainingState_LSB 0x0
#define QIB_7322_IBCStatusA_0_LinkTrainingState_MSB 0x4
#define QIB_7322_IBCStatusA_0_LinkTrainingState_RMASK 0x1F

#define QIB_7322_IBCStatusB_0_OFFS 0x1548
#define QIB_7322_IBCStatusB_0_DEF 0x00000000XXXXXXXX
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_LSB 0x27
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_MSB 0x27
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_RMASK 0x1
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_LSB 0x26
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_MSB 0x26
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_RMASK 0x1
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_LSB 0x25
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_MSB 0x25
#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_RMASK 0x1
#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_LSB 0x24
#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_MSB 0x24
#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_RMASK 0x1
#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_LSB 0x20
#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_MSB 0x23
#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_RMASK 0xF
#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_LSB 0x1E
#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_MSB 0x1F
#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_RMASK 0x3
#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_LSB 0x1A
#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_MSB 0x1D
#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_RMASK 0xF
#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_LSB 0x0
#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_MSB 0x19
#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_RMASK 0x3FFFFFF

#define QIB_7322_IBCCtrlA_0_OFFS 0x1560
#define QIB_7322_IBCCtrlA_0_DEF 0x0000000000000000
#define QIB_7322_IBCCtrlA_0_Loopback_LSB 0x3F
#define QIB_7322_IBCCtrlA_0_Loopback_MSB 0x3F
#define QIB_7322_IBCCtrlA_0_Loopback_RMASK 0x1
#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_LSB 0x3E
#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_MSB 0x3E
#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_RMASK 0x1
#define QIB_7322_IBCCtrlA_0_IBLinkEn_LSB 0x3D
#define QIB_7322_IBCCtrlA_0_IBLinkEn_MSB 0x3D
#define QIB_7322_IBCCtrlA_0_IBLinkEn_RMASK 0x1
#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_LSB 0x3C
#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_MSB 0x3C
#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_RMASK 0x1
#define QIB_7322_IBCCtrlA_0_NumVLane_LSB 0x30
#define QIB_7322_IBCCtrlA_0_NumVLane_MSB 0x32
#define QIB_7322_IBCCtrlA_0_NumVLane_RMASK 0x7
#define QIB_7322_IBCCtrlA_0_OverrunThreshold_LSB 0x24
#define QIB_7322_IBCCtrlA_0_OverrunThreshold_MSB 0x27
#define QIB_7322_IBCCtrlA_0_OverrunThreshold_RMASK 0xF
#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_LSB 0x20
#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_MSB 0x23
#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_RMASK 0xF
#define QIB_7322_IBCCtrlA_0_MaxPktLen_LSB 0x15
#define QIB_7322_IBCCtrlA_0_MaxPktLen_MSB 0x1F
#define QIB_7322_IBCCtrlA_0_MaxPktLen_RMASK 0x7FF
#define QIB_7322_IBCCtrlA_0_LinkCmd_LSB 0x13
#define QIB_7322_IBCCtrlA_0_LinkCmd_MSB 0x14
#define QIB_7322_IBCCtrlA_0_LinkCmd_RMASK 0x3
#define QIB_7322_IBCCtrlA_0_LinkInitCmd_LSB 0x10
#define QIB_7322_IBCCtrlA_0_LinkInitCmd_MSB 0x12
#define QIB_7322_IBCCtrlA_0_LinkInitCmd_RMASK 0x7
#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_LSB 0x8
#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_MSB 0xF
#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_RMASK 0xFF
#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_LSB 0x0
#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_MSB 0x7
#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_RMASK 0xFF

#define QIB_7322_IBCCtrlB_0_OFFS 0x1568
#define QIB_7322_IBCCtrlB_0_DEF 0x00000000000305FF
#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_LSB 0x30
#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_MSB 0x3F
#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK 0xFFFF
#define QIB_7322_IBCCtrlB_0_IB_DLID_LSB 0x20
#define QIB_7322_IBCCtrlB_0_IB_DLID_MSB 0x2F
#define QIB_7322_IBCCtrlB_0_IB_DLID_RMASK 0xFFFF
#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_LSB 0x1B
#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_MSB 0x1B
#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_LSB 0x1A
#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_MSB 0x1A
#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_LSB 0x12
#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_MSB 0x19
#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_RMASK 0xFF
#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_LSB 0x11
#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_MSB 0x11
#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_LSB 0x10
#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_MSB 0x10
#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_SD_DDS_LSB 0xC
#define QIB_7322_IBCCtrlB_0_SD_DDS_MSB 0xF
#define QIB_7322_IBCCtrlB_0_SD_DDS_RMASK 0xF
#define QIB_7322_IBCCtrlB_0_SD_DDSV_LSB 0xB
#define QIB_7322_IBCCtrlB_0_SD_DDSV_MSB 0xB
#define QIB_7322_IBCCtrlB_0_SD_DDSV_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_LSB 0xA
#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_MSB 0xA
#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_LSB 0x9
#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_MSB 0x9
#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_LSB 0x8
#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_MSB 0x8
#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_LSB 0x7
#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_MSB 0x7
#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_LSB 0x5
#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_MSB 0x6
#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_RMASK 0x3
#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_LSB 0x4
#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_MSB 0x4
#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_LSB 0x3
#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_MSB 0x3
#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_LSB 0x2
#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_MSB 0x2
#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_SD_SPEED_LSB 0x1
#define QIB_7322_IBCCtrlB_0_SD_SPEED_MSB 0x1
#define QIB_7322_IBCCtrlB_0_SD_SPEED_RMASK 0x1
#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_LSB 0x0
#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_MSB 0x0
#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_RMASK 0x1

#define QIB_7322_IBCCtrlC_0_OFFS 0x1570
#define QIB_7322_IBCCtrlC_0_DEF 0x0000000000000301
#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_LSB 0x5
#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_MSB 0x9
#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_RMASK 0x1F
#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_LSB 0x0
#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_MSB 0x4
#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_RMASK 0x1F

#define QIB_7322_HRTBT_GUID_0_OFFS 0x1588
#define QIB_7322_HRTBT_GUID_0_DEF 0x0000000000000000

#define QIB_7322_IB_SDTEST_IF_TX_0_OFFS 0x1590
#define QIB_7322_IB_SDTEST_IF_TX_0_DEF 0x0000000000000000
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_LSB 0x30
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_MSB 0x3F
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_LSB 0x20
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_MSB 0x2F
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_LSB 0xD
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_MSB 0xF
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_RMASK 0x7
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_LSB 0xB
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_MSB 0xC
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_RMASK 0x3
#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_LSB 0x4
#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_MSB 0x4
#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_RMASK 0x1
#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_LSB 0x2
#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_MSB 0x3
#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_RMASK 0x3
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_LSB 0x1
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_MSB 0x1
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_RMASK 0x1
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_LSB 0x0
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_MSB 0x0
#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_RMASK 0x1

#define QIB_7322_IB_SDTEST_IF_RX_0_OFFS 0x1598
#define QIB_7322_IB_SDTEST_IF_RX_0_DEF 0x0000000000000000
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_LSB 0x30
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_MSB 0x3F
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_LSB 0x20
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_MSB 0x2F
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_LSB 0x18
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_MSB 0x1F
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_RMASK 0xFF
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_LSB 0x10
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_MSB 0x17
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_RMASK 0xFF
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_LSB 0x1
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_MSB 0x1
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_RMASK 0x1
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_LSB 0x0
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_MSB 0x0
#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_RMASK 0x1

#define QIB_7322_IBNCModeCtrl_0_OFFS 0x15B8
#define QIB_7322_IBNCModeCtrl_0_DEF 0x0000000000000000
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_LSB 0x22
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_MSB 0x22
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_LSB 0x21
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_MSB 0x21
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_LSB 0x20
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_MSB 0x20
#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_LSB 0x11
#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_MSB 0x19
#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_RMASK 0x1FF
#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_LSB 0x8
#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_MSB 0x10
#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_RMASK 0x1FF
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_LSB 0x2
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_MSB 0x2
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_LSB 0x1
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_MSB 0x1
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_LSB 0x0
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_MSB 0x0
#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_RMASK 0x1

#define QIB_7322_IBSerdesStatus_0_OFFS 0x15D0
#define QIB_7322_IBSerdesStatus_0_DEF 0x0000000000000000

#define QIB_7322_IBPCSConfig_0_OFFS 0x15D8
#define QIB_7322_IBPCSConfig_0_DEF 0x0000000000000007
#define QIB_7322_IBPCSConfig_0_link_sync_mask_LSB 0x9
#define QIB_7322_IBPCSConfig_0_link_sync_mask_MSB 0x12
#define QIB_7322_IBPCSConfig_0_link_sync_mask_RMASK 0x3FF
#define QIB_7322_IBPCSConfig_0_xcv_rreset_LSB 0x2
#define QIB_7322_IBPCSConfig_0_xcv_rreset_MSB 0x2
#define QIB_7322_IBPCSConfig_0_xcv_rreset_RMASK 0x1
#define QIB_7322_IBPCSConfig_0_xcv_treset_LSB 0x1
#define QIB_7322_IBPCSConfig_0_xcv_treset_MSB 0x1
#define QIB_7322_IBPCSConfig_0_xcv_treset_RMASK 0x1
#define QIB_7322_IBPCSConfig_0_tx_rx_reset_LSB 0x0
#define QIB_7322_IBPCSConfig_0_tx_rx_reset_MSB 0x0
#define QIB_7322_IBPCSConfig_0_tx_rx_reset_RMASK 0x1

#define QIB_7322_IBSerdesCtrl_0_OFFS 0x15E0
#define QIB_7322_IBSerdesCtrl_0_DEF 0x0000000000FFA00F
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_LSB 0x1A
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_MSB 0x1A
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_LSB 0x19
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_MSB 0x19
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_LSB 0x18
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_MSB 0x18
#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_LSB 0x14
#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_MSB 0x17
#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_RMASK 0xF
#define QIB_7322_IBSerdesCtrl_0_CGMODE_LSB 0x10
#define QIB_7322_IBSerdesCtrl_0_CGMODE_MSB 0x13
#define QIB_7322_IBSerdesCtrl_0_CGMODE_RMASK 0xF
#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_LSB 0xF
#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_MSB 0xF
#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_LSB 0xD
#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_MSB 0xD
#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_LPEN_LSB 0xC
#define QIB_7322_IBSerdesCtrl_0_LPEN_MSB 0xC
#define QIB_7322_IBSerdesCtrl_0_LPEN_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_PLLPD_LSB 0xB
#define QIB_7322_IBSerdesCtrl_0_PLLPD_MSB 0xB
#define QIB_7322_IBSerdesCtrl_0_PLLPD_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_TXPD_LSB 0xA
#define QIB_7322_IBSerdesCtrl_0_TXPD_MSB 0xA
#define QIB_7322_IBSerdesCtrl_0_TXPD_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_RXPD_LSB 0x9
#define QIB_7322_IBSerdesCtrl_0_RXPD_MSB 0x9
#define QIB_7322_IBSerdesCtrl_0_RXPD_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_TXIDLE_LSB 0x8
#define QIB_7322_IBSerdesCtrl_0_TXIDLE_MSB 0x8
#define QIB_7322_IBSerdesCtrl_0_TXIDLE_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_0_CMODE_LSB 0x0
#define QIB_7322_IBSerdesCtrl_0_CMODE_MSB 0x6
#define QIB_7322_IBSerdesCtrl_0_CMODE_RMASK 0x7F

#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_OFFS 0x1600
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_DEF 0x0000000000000000
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_LSB 0x1F
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_MSB 0x1F
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_RMASK 0x1
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_LSB 0x1E
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_MSB 0x1E
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_RMASK 0x1
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_LSB 0xE
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_MSB 0x11
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_RMASK 0xF
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_LSB 0x9
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_MSB 0xD
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_RMASK 0x1F
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_LSB 0x5
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_MSB 0x8
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_RMASK 0xF
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_LSB 0x3
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_MSB 0x4
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_RMASK 0x3
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_LSB 0x0
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_MSB 0x2
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_RMASK 0x7

#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_OFFS 0x1640
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_OFFS 0x1648
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_OFFS 0x1650
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_OFFS 0x1658
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_OFFS 0x1660
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_OFFS 0x1668
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_OFFS 0x1670
#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_DEF 0x0000000000000000

#define QIB_7322_RxBufrUnCorErrLogA_0_OFFS 0x1800
#define QIB_7322_RxBufrUnCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogA_0_RxBufrUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogA_0_RxBufrUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogA_0_RxBufrUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogB_0_OFFS 0x1808
#define QIB_7322_RxBufrUnCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogB_0_RxBufrUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogB_0_RxBufrUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogB_0_RxBufrUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogC_0_OFFS 0x1810
#define QIB_7322_RxBufrUnCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogC_0_RxBufrUnCorErrData_191_128_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogC_0_RxBufrUnCorErrData_191_128_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogC_0_RxBufrUnCorErrData_191_128_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogD_0_OFFS 0x1818
#define QIB_7322_RxBufrUnCorErrLogD_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogD_0_RxBufrUnCorErrData_255_192_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogD_0_RxBufrUnCorErrData_255_192_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogD_0_RxBufrUnCorErrData_255_192_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogE_0_OFFS 0x1820
#define QIB_7322_RxBufrUnCorErrLogE_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrAddr_15_0_LSB 0x28
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrAddr_15_0_MSB 0x37
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrAddr_15_0_RMASK 0xFFFF
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrCheckBit_36_0_LSB 0x3
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrCheckBit_36_0_MSB 0x27
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrCheckBit_36_0_RMASK 0x1FFFFFFFFF
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrData_258_256_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrData_258_256_MSB 0x2
#define QIB_7322_RxBufrUnCorErrLogE_0_RxBufrUnCorErrData_258_256_RMASK 0x7

#define QIB_7322_RxFlagUnCorErrLogA_0_OFFS 0x1828
#define QIB_7322_RxFlagUnCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxFlagUnCorErrLogA_0_RxFlagUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxFlagUnCorErrLogA_0_RxFlagUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxFlagUnCorErrLogA_0_RxFlagUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxFlagUnCorErrLogB_0_OFFS 0x1830
#define QIB_7322_RxFlagUnCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxFlagUnCorErrLogB_0_RxFlagUnCorErrAddr_12_0_LSB 0x8
#define QIB_7322_RxFlagUnCorErrLogB_0_RxFlagUnCorErrAddr_12_0_MSB 0x14
#define QIB_7322_RxFlagUnCorErrLogB_0_RxFlagUnCorErrAddr_12_0_RMASK 0x1FFF
#define QIB_7322_RxFlagUnCorErrLogB_0_RxFlagUnCorErrCheckBit_7_0_LSB 0x0
#define QIB_7322_RxFlagUnCorErrLogB_0_RxFlagUnCorErrCheckBit_7_0_MSB 0x7
#define QIB_7322_RxFlagUnCorErrLogB_0_RxFlagUnCorErrCheckBit_7_0_RMASK 0xFF

#define QIB_7322_RxLkupiqUnCorErrLogA_0_OFFS 0x1840
#define QIB_7322_RxLkupiqUnCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqUnCorErrLogA_0_RxLkupiqUnCorErrCheckBit_7_0_LSB 0x2E
#define QIB_7322_RxLkupiqUnCorErrLogA_0_RxLkupiqUnCorErrCheckBit_7_0_MSB 0x35
#define QIB_7322_RxLkupiqUnCorErrLogA_0_RxLkupiqUnCorErrCheckBit_7_0_RMASK 0xFF
#define QIB_7322_RxLkupiqUnCorErrLogA_0_RxLkupiqUnCorErrData_45_0_LSB 0x0
#define QIB_7322_RxLkupiqUnCorErrLogA_0_RxLkupiqUnCorErrData_45_0_MSB 0x2D
#define QIB_7322_RxLkupiqUnCorErrLogA_0_RxLkupiqUnCorErrData_45_0_RMASK 0x3FFFFFFFFFFF

#define QIB_7322_RxLkupiqUnCorErrLogB_0_OFFS 0x1848
#define QIB_7322_RxLkupiqUnCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqUnCorErrLogB_0_RxLkupiqUnCorErrAddr_12_0_LSB 0x0
#define QIB_7322_RxLkupiqUnCorErrLogB_0_RxLkupiqUnCorErrAddr_12_0_MSB 0xC
#define QIB_7322_RxLkupiqUnCorErrLogB_0_RxLkupiqUnCorErrAddr_12_0_RMASK 0x1FFF

#define QIB_7322_RxHdrFifoUnCorErrLogA_0_OFFS 0x1850
#define QIB_7322_RxHdrFifoUnCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoUnCorErrLogA_0_RxHdrFifoUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxHdrFifoUnCorErrLogA_0_RxHdrFifoUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxHdrFifoUnCorErrLogA_0_RxHdrFifoUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxHdrFifoUnCorErrLogB_0_OFFS 0x1858
#define QIB_7322_RxHdrFifoUnCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoUnCorErrLogB_0_RxHdrFifoUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RxHdrFifoUnCorErrLogB_0_RxHdrFifoUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxHdrFifoUnCorErrLogB_0_RxHdrFifoUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxHdrFifoUnCorErrLogC_0_OFFS 0x1860
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_RxHdrFifoUnCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_RxHdrFifoUnCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_RxHdrFifoUnCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_RxHdrFifoUnCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_RxHdrFifoUnCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxHdrFifoUnCorErrLogC_0_RxHdrFifoUnCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_RxDataFifoUnCorErrLogA_0_OFFS 0x1868
#define QIB_7322_RxDataFifoUnCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoUnCorErrLogA_0_RxDataFifoUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxDataFifoUnCorErrLogA_0_RxDataFifoUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxDataFifoUnCorErrLogA_0_RxDataFifoUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxDataFifoUnCorErrLogB_0_OFFS 0x1870
#define QIB_7322_RxDataFifoUnCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoUnCorErrLogB_0_RxDataFifoUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RxDataFifoUnCorErrLogB_0_RxDataFifoUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxDataFifoUnCorErrLogB_0_RxDataFifoUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxDataFifoUnCorErrLogC_0_OFFS 0x1878
#define QIB_7322_RxDataFifoUnCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoUnCorErrLogC_0_RxDataFifoUnCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxDataFifoUnCorErrLogC_0_RxDataFifoUnCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxDataFifoUnCorErrLogC_0_RxDataFifoUnCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxDataFifoUnCorErrLogC_0_RxDataFifoUnCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxDataFifoUnCorErrLogC_0_RxDataFifoUnCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxDataFifoUnCorErrLogC_0_RxDataFifoUnCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_LaFifoArray0UnCorErrLog_0_OFFS 0x1880
#define QIB_7322_LaFifoArray0UnCorErrLog_0_DEF 0x0000000000000000
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrAddr_10_0_LSB 0x2E
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrAddr_10_0_MSB 0x38
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrCheckBit_10_0_LSB 0x23
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrCheckBit_10_0_MSB 0x2D
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrCheckBit_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrData_34_0_LSB 0x0
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrData_34_0_MSB 0x22
#define QIB_7322_LaFifoArray0UnCorErrLog_0_LaFifoArray0UnCorErrData_34_0_RMASK 0x7FFFFFFFF

#define QIB_7322_RmFifoArrayUnCorErrLogA_0_OFFS 0x18C0
#define QIB_7322_RmFifoArrayUnCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayUnCorErrLogA_0_RmFifoArrayUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RmFifoArrayUnCorErrLogA_0_RmFifoArrayUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RmFifoArrayUnCorErrLogA_0_RmFifoArrayUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RmFifoArrayUnCorErrLogB_0_OFFS 0x18C8
#define QIB_7322_RmFifoArrayUnCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayUnCorErrLogB_0_RmFifoArrayUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RmFifoArrayUnCorErrLogB_0_RmFifoArrayUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RmFifoArrayUnCorErrLogB_0_RmFifoArrayUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RmFifoArrayUnCorErrLogC_0_OFFS 0x18D0
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrDword_3_0_LSB 0x3C
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrDword_3_0_MSB 0x3F
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrDword_3_0_RMASK 0xF
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrAddr_13_0_LSB 0x1C
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrAddr_13_0_MSB 0x29
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_RmFifoArrayUnCorErrLogC_0_RmFifoArrayUnCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_RxBufrCorErrLogA_0_OFFS 0x1900
#define QIB_7322_RxBufrCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogA_0_RxBufrCorErrData_63_0_LSB 0x0
#define QIB_7322_RxBufrCorErrLogA_0_RxBufrCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogA_0_RxBufrCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogB_0_OFFS 0x1908
#define QIB_7322_RxBufrCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogB_0_RxBufrCorErrData_127_64_LSB 0x0
#define QIB_7322_RxBufrCorErrLogB_0_RxBufrCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogB_0_RxBufrCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogC_0_OFFS 0x1910
#define QIB_7322_RxBufrCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogC_0_RxBufrCorErrData_191_128_LSB 0x0
#define QIB_7322_RxBufrCorErrLogC_0_RxBufrCorErrData_191_128_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogC_0_RxBufrCorErrData_191_128_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogD_0_OFFS 0x1918
#define QIB_7322_RxBufrCorErrLogD_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogD_0_RxBufrCorErrData_255_192_LSB 0x0
#define QIB_7322_RxBufrCorErrLogD_0_RxBufrCorErrData_255_192_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogD_0_RxBufrCorErrData_255_192_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogE_0_OFFS 0x1920
#define QIB_7322_RxBufrCorErrLogE_0_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrAddr_15_0_LSB 0x28
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrAddr_15_0_MSB 0x37
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrAddr_15_0_RMASK 0xFFFF
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrCheckBit_36_0_LSB 0x3
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrCheckBit_36_0_MSB 0x27
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrCheckBit_36_0_RMASK 0x1FFFFFFFFF
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrData_258_256_LSB 0x0
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrData_258_256_MSB 0x2
#define QIB_7322_RxBufrCorErrLogE_0_RxBufrCorErrData_258_256_RMASK 0x7

#define QIB_7322_RxFlagCorErrLogA_0_OFFS 0x1928
#define QIB_7322_RxFlagCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxFlagCorErrLogA_0_RxFlagCorErrData_63_0_LSB 0x0
#define QIB_7322_RxFlagCorErrLogA_0_RxFlagCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxFlagCorErrLogA_0_RxFlagCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxFlagCorErrLogB_0_OFFS 0x1930
#define QIB_7322_RxFlagCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxFlagCorErrLogB_0_RxFlagCorErrAddr_12_0_LSB 0x8
#define QIB_7322_RxFlagCorErrLogB_0_RxFlagCorErrAddr_12_0_MSB 0x14
#define QIB_7322_RxFlagCorErrLogB_0_RxFlagCorErrAddr_12_0_RMASK 0x1FFF
#define QIB_7322_RxFlagCorErrLogB_0_RxFlagCorErrCheckBit_7_0_LSB 0x0
#define QIB_7322_RxFlagCorErrLogB_0_RxFlagCorErrCheckBit_7_0_MSB 0x7
#define QIB_7322_RxFlagCorErrLogB_0_RxFlagCorErrCheckBit_7_0_RMASK 0xFF

#define QIB_7322_RxLkupiqCorErrLogA_0_OFFS 0x1940
#define QIB_7322_RxLkupiqCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqCorErrLogA_0_RxLkupiqCorErrCheckBit_7_0_LSB 0x2E
#define QIB_7322_RxLkupiqCorErrLogA_0_RxLkupiqCorErrCheckBit_7_0_MSB 0x35
#define QIB_7322_RxLkupiqCorErrLogA_0_RxLkupiqCorErrCheckBit_7_0_RMASK 0xFF
#define QIB_7322_RxLkupiqCorErrLogA_0_RxLkupiqCorErrData_45_0_LSB 0x0
#define QIB_7322_RxLkupiqCorErrLogA_0_RxLkupiqCorErrData_45_0_MSB 0x2D
#define QIB_7322_RxLkupiqCorErrLogA_0_RxLkupiqCorErrData_45_0_RMASK 0x3FFFFFFFFFFF

#define QIB_7322_RxLkupiqCorErrLogB_0_OFFS 0x1948
#define QIB_7322_RxLkupiqCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqCorErrLogB_0_RxLkupiqCorErrAddr_12_0_LSB 0x0
#define QIB_7322_RxLkupiqCorErrLogB_0_RxLkupiqCorErrAddr_12_0_MSB 0xC
#define QIB_7322_RxLkupiqCorErrLogB_0_RxLkupiqCorErrAddr_12_0_RMASK 0x1FFF

#define QIB_7322_RxHdrFifoCorErrLogA_0_OFFS 0x1950
#define QIB_7322_RxHdrFifoCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoCorErrLogA_0_RxHdrFifoCorErrData_63_0_LSB 0x0
#define QIB_7322_RxHdrFifoCorErrLogA_0_RxHdrFifoCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxHdrFifoCorErrLogA_0_RxHdrFifoCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxHdrFifoCorErrLogB_0_OFFS 0x1958
#define QIB_7322_RxHdrFifoCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoCorErrLogB_0_RxHdrFifoCorErrData_127_64_LSB 0x0
#define QIB_7322_RxHdrFifoCorErrLogB_0_RxHdrFifoCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxHdrFifoCorErrLogB_0_RxHdrFifoCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxHdrFifoCorErrLogC_0_OFFS 0x1960
#define QIB_7322_RxHdrFifoCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoCorErrLogC_0_RxHdrFifoCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxHdrFifoCorErrLogC_0_RxHdrFifoCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxHdrFifoCorErrLogC_0_RxHdrFifoCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxHdrFifoCorErrLogC_0_RxHdrFifoCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxHdrFifoCorErrLogC_0_RxHdrFifoCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxHdrFifoCorErrLogC_0_RxHdrFifoCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_RxDataFifoCorErrLogA_0_OFFS 0x1968
#define QIB_7322_RxDataFifoCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoCorErrLogA_0_RxDataFifoCorErrData_63_0_LSB 0x0
#define QIB_7322_RxDataFifoCorErrLogA_0_RxDataFifoCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxDataFifoCorErrLogA_0_RxDataFifoCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxDataFifoCorErrLogB_0_OFFS 0x1970
#define QIB_7322_RxDataFifoCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoCorErrLogB_0_RxDataFifoCorErrData_127_64_LSB 0x0
#define QIB_7322_RxDataFifoCorErrLogB_0_RxDataFifoCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxDataFifoCorErrLogB_0_RxDataFifoCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxDataFifoCorErrLogC_0_OFFS 0x1978
#define QIB_7322_RxDataFifoCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoCorErrLogC_0_RxDataFifoCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxDataFifoCorErrLogC_0_RxDataFifoCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxDataFifoCorErrLogC_0_RxDataFifoCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxDataFifoCorErrLogC_0_RxDataFifoCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxDataFifoCorErrLogC_0_RxDataFifoCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxDataFifoCorErrLogC_0_RxDataFifoCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_LaFifoArray0CorErrLog_0_OFFS 0x1980
#define QIB_7322_LaFifoArray0CorErrLog_0_DEF 0x0000000000000000
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrAddr_10_0_LSB 0x2E
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrAddr_10_0_MSB 0x38
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrCheckBit_10_0_LSB 0x23
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrCheckBit_10_0_MSB 0x2D
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrCheckBit_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrData_34_0_LSB 0x0
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrData_34_0_MSB 0x22
#define QIB_7322_LaFifoArray0CorErrLog_0_LaFifoArray0CorErrData_34_0_RMASK 0x7FFFFFFFF

#define QIB_7322_RmFifoArrayCorErrLogA_0_OFFS 0x19C0
#define QIB_7322_RmFifoArrayCorErrLogA_0_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayCorErrLogA_0_RmFifoArrayCorErrData_63_0_LSB 0x0
#define QIB_7322_RmFifoArrayCorErrLogA_0_RmFifoArrayCorErrData_63_0_MSB 0x3F
#define QIB_7322_RmFifoArrayCorErrLogA_0_RmFifoArrayCorErrData_63_0_RMASK 0x0

#define QIB_7322_RmFifoArrayCorErrLogB_0_OFFS 0x19C8
#define QIB_7322_RmFifoArrayCorErrLogB_0_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayCorErrLogB_0_RmFifoArrayCorErrData_127_64_LSB 0x0
#define QIB_7322_RmFifoArrayCorErrLogB_0_RmFifoArrayCorErrData_127_64_MSB 0x3F
#define QIB_7322_RmFifoArrayCorErrLogB_0_RmFifoArrayCorErrData_127_64_RMASK 0x0

#define QIB_7322_RmFifoArrayCorErrLogC_0_OFFS 0x19D0
#define QIB_7322_RmFifoArrayCorErrLogC_0_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrDword_3_0_LSB 0x3C
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrDword_3_0_MSB 0x3F
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrDword_3_0_RMASK 0xF
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrAddr_13_0_LSB 0x1C
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrAddr_13_0_MSB 0x29
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_RmFifoArrayCorErrLogC_0_RmFifoArrayCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_HighPriorityLimit_0_OFFS 0x1BC0
#define QIB_7322_HighPriorityLimit_0_DEF 0x0000000000000000
#define QIB_7322_HighPriorityLimit_0_Limit_LSB 0x0
#define QIB_7322_HighPriorityLimit_0_Limit_MSB 0x7
#define QIB_7322_HighPriorityLimit_0_Limit_RMASK 0xFF

#define QIB_7322_LowPriority0_0_OFFS 0x1C00
#define QIB_7322_LowPriority0_0_DEF 0x0000000000000000
#define QIB_7322_LowPriority0_0_VirtualLane_LSB 0x10
#define QIB_7322_LowPriority0_0_VirtualLane_MSB 0x12
#define QIB_7322_LowPriority0_0_VirtualLane_RMASK 0x7
#define QIB_7322_LowPriority0_0_Weight_LSB 0x0
#define QIB_7322_LowPriority0_0_Weight_MSB 0x7
#define QIB_7322_LowPriority0_0_Weight_RMASK 0xFF

#define QIB_7322_HighPriority0_0_OFFS 0x1E00
#define QIB_7322_HighPriority0_0_DEF 0x0000000000000000
#define QIB_7322_HighPriority0_0_VirtualLane_LSB 0x10
#define QIB_7322_HighPriority0_0_VirtualLane_MSB 0x12
#define QIB_7322_HighPriority0_0_VirtualLane_RMASK 0x7
#define QIB_7322_HighPriority0_0_Weight_LSB 0x0
#define QIB_7322_HighPriority0_0_Weight_MSB 0x7
#define QIB_7322_HighPriority0_0_Weight_RMASK 0xFF

#define QIB_7322_CntrRegBase_1_OFFS 0x2028
#define QIB_7322_CntrRegBase_1_DEF 0x0000000000013000

#define QIB_7322_ErrMask_1_OFFS 0x2080
#define QIB_7322_ErrMask_1_DEF 0x0000000000000000
#define QIB_7322_ErrMask_1_IBStatusChangedMask_LSB 0x3A
#define QIB_7322_ErrMask_1_IBStatusChangedMask_MSB 0x3A
#define QIB_7322_ErrMask_1_IBStatusChangedMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SHeadersErrMask_LSB 0x39
#define QIB_7322_ErrMask_1_SHeadersErrMask_MSB 0x39
#define QIB_7322_ErrMask_1_SHeadersErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_VL15BufMisuseErrMask_LSB 0x36
#define QIB_7322_ErrMask_1_VL15BufMisuseErrMask_MSB 0x36
#define QIB_7322_ErrMask_1_VL15BufMisuseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaHaltErrMask_LSB 0x31
#define QIB_7322_ErrMask_1_SDmaHaltErrMask_MSB 0x31
#define QIB_7322_ErrMask_1_SDmaHaltErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaDescAddrMisalignErrMask_LSB 0x30
#define QIB_7322_ErrMask_1_SDmaDescAddrMisalignErrMask_MSB 0x30
#define QIB_7322_ErrMask_1_SDmaDescAddrMisalignErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaUnexpDataErrMask_LSB 0x2F
#define QIB_7322_ErrMask_1_SDmaUnexpDataErrMask_MSB 0x2F
#define QIB_7322_ErrMask_1_SDmaUnexpDataErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaMissingDwErrMask_LSB 0x2E
#define QIB_7322_ErrMask_1_SDmaMissingDwErrMask_MSB 0x2E
#define QIB_7322_ErrMask_1_SDmaMissingDwErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaDwEnErrMask_LSB 0x2D
#define QIB_7322_ErrMask_1_SDmaDwEnErrMask_MSB 0x2D
#define QIB_7322_ErrMask_1_SDmaDwEnErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaRpyTagErrMask_LSB 0x2C
#define QIB_7322_ErrMask_1_SDmaRpyTagErrMask_MSB 0x2C
#define QIB_7322_ErrMask_1_SDmaRpyTagErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDma1stDescErrMask_LSB 0x2B
#define QIB_7322_ErrMask_1_SDma1stDescErrMask_MSB 0x2B
#define QIB_7322_ErrMask_1_SDma1stDescErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaBaseErrMask_LSB 0x2A
#define QIB_7322_ErrMask_1_SDmaBaseErrMask_MSB 0x2A
#define QIB_7322_ErrMask_1_SDmaBaseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaTailOutOfBoundErrMask_LSB 0x29
#define QIB_7322_ErrMask_1_SDmaTailOutOfBoundErrMask_MSB 0x29
#define QIB_7322_ErrMask_1_SDmaTailOutOfBoundErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaOutOfBoundErrMask_LSB 0x28
#define QIB_7322_ErrMask_1_SDmaOutOfBoundErrMask_MSB 0x28
#define QIB_7322_ErrMask_1_SDmaOutOfBoundErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SDmaGenMismatchErrMask_LSB 0x27
#define QIB_7322_ErrMask_1_SDmaGenMismatchErrMask_MSB 0x27
#define QIB_7322_ErrMask_1_SDmaGenMismatchErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendBufMisuseErrMask_LSB 0x26
#define QIB_7322_ErrMask_1_SendBufMisuseErrMask_MSB 0x26
#define QIB_7322_ErrMask_1_SendBufMisuseErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendUnsupportedVLErrMask_LSB 0x25
#define QIB_7322_ErrMask_1_SendUnsupportedVLErrMask_MSB 0x25
#define QIB_7322_ErrMask_1_SendUnsupportedVLErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendUnexpectedPktNumErrMask_LSB 0x24
#define QIB_7322_ErrMask_1_SendUnexpectedPktNumErrMask_MSB 0x24
#define QIB_7322_ErrMask_1_SendUnexpectedPktNumErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendDroppedDataPktErrMask_LSB 0x22
#define QIB_7322_ErrMask_1_SendDroppedDataPktErrMask_MSB 0x22
#define QIB_7322_ErrMask_1_SendDroppedDataPktErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendDroppedSmpPktErrMask_LSB 0x21
#define QIB_7322_ErrMask_1_SendDroppedSmpPktErrMask_MSB 0x21
#define QIB_7322_ErrMask_1_SendDroppedSmpPktErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendPktLenErrMask_LSB 0x20
#define QIB_7322_ErrMask_1_SendPktLenErrMask_MSB 0x20
#define QIB_7322_ErrMask_1_SendPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendUnderRunErrMask_LSB 0x1F
#define QIB_7322_ErrMask_1_SendUnderRunErrMask_MSB 0x1F
#define QIB_7322_ErrMask_1_SendUnderRunErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendMaxPktLenErrMask_LSB 0x1E
#define QIB_7322_ErrMask_1_SendMaxPktLenErrMask_MSB 0x1E
#define QIB_7322_ErrMask_1_SendMaxPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_SendMinPktLenErrMask_LSB 0x1D
#define QIB_7322_ErrMask_1_SendMinPktLenErrMask_MSB 0x1D
#define QIB_7322_ErrMask_1_SendMinPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvIBLostLinkErrMask_LSB 0x11
#define QIB_7322_ErrMask_1_RcvIBLostLinkErrMask_MSB 0x11
#define QIB_7322_ErrMask_1_RcvIBLostLinkErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvHdrErrMask_LSB 0x10
#define QIB_7322_ErrMask_1_RcvHdrErrMask_MSB 0x10
#define QIB_7322_ErrMask_1_RcvHdrErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvHdrLenErrMask_LSB 0xF
#define QIB_7322_ErrMask_1_RcvHdrLenErrMask_MSB 0xF
#define QIB_7322_ErrMask_1_RcvHdrLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvBadTidErrMask_LSB 0xE
#define QIB_7322_ErrMask_1_RcvBadTidErrMask_MSB 0xE
#define QIB_7322_ErrMask_1_RcvBadTidErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvBadVersionErrMask_LSB 0xB
#define QIB_7322_ErrMask_1_RcvBadVersionErrMask_MSB 0xB
#define QIB_7322_ErrMask_1_RcvBadVersionErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvIBFlowErrMask_LSB 0xA
#define QIB_7322_ErrMask_1_RcvIBFlowErrMask_MSB 0xA
#define QIB_7322_ErrMask_1_RcvIBFlowErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvEBPErrMask_LSB 0x9
#define QIB_7322_ErrMask_1_RcvEBPErrMask_MSB 0x9
#define QIB_7322_ErrMask_1_RcvEBPErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvUnsupportedVLErrMask_LSB 0x8
#define QIB_7322_ErrMask_1_RcvUnsupportedVLErrMask_MSB 0x8
#define QIB_7322_ErrMask_1_RcvUnsupportedVLErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvUnexpectedCharErrMask_LSB 0x7
#define QIB_7322_ErrMask_1_RcvUnexpectedCharErrMask_MSB 0x7
#define QIB_7322_ErrMask_1_RcvUnexpectedCharErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvShortPktLenErrMask_LSB 0x6
#define QIB_7322_ErrMask_1_RcvShortPktLenErrMask_MSB 0x6
#define QIB_7322_ErrMask_1_RcvShortPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvLongPktLenErrMask_LSB 0x5
#define QIB_7322_ErrMask_1_RcvLongPktLenErrMask_MSB 0x5
#define QIB_7322_ErrMask_1_RcvLongPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvMaxPktLenErrMask_LSB 0x4
#define QIB_7322_ErrMask_1_RcvMaxPktLenErrMask_MSB 0x4
#define QIB_7322_ErrMask_1_RcvMaxPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvMinPktLenErrMask_LSB 0x3
#define QIB_7322_ErrMask_1_RcvMinPktLenErrMask_MSB 0x3
#define QIB_7322_ErrMask_1_RcvMinPktLenErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvICRCErrMask_LSB 0x2
#define QIB_7322_ErrMask_1_RcvICRCErrMask_MSB 0x2
#define QIB_7322_ErrMask_1_RcvICRCErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvVCRCErrMask_LSB 0x1
#define QIB_7322_ErrMask_1_RcvVCRCErrMask_MSB 0x1
#define QIB_7322_ErrMask_1_RcvVCRCErrMask_RMASK 0x1
#define QIB_7322_ErrMask_1_RcvFormatErrMask_LSB 0x0
#define QIB_7322_ErrMask_1_RcvFormatErrMask_MSB 0x0
#define QIB_7322_ErrMask_1_RcvFormatErrMask_RMASK 0x1

#define QIB_7322_ErrStatus_1_OFFS 0x2088
#define QIB_7322_ErrStatus_1_DEF 0x0000000000000000
#define QIB_7322_ErrStatus_1_IBStatusChanged_LSB 0x3A
#define QIB_7322_ErrStatus_1_IBStatusChanged_MSB 0x3A
#define QIB_7322_ErrStatus_1_IBStatusChanged_RMASK 0x1
#define QIB_7322_ErrStatus_1_SHeadersErr_LSB 0x39
#define QIB_7322_ErrStatus_1_SHeadersErr_MSB 0x39
#define QIB_7322_ErrStatus_1_SHeadersErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_VL15BufMisuseErr_LSB 0x36
#define QIB_7322_ErrStatus_1_VL15BufMisuseErr_MSB 0x36
#define QIB_7322_ErrStatus_1_VL15BufMisuseErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaHaltErr_LSB 0x31
#define QIB_7322_ErrStatus_1_SDmaHaltErr_MSB 0x31
#define QIB_7322_ErrStatus_1_SDmaHaltErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaDescAddrMisalignErr_LSB 0x30
#define QIB_7322_ErrStatus_1_SDmaDescAddrMisalignErr_MSB 0x30
#define QIB_7322_ErrStatus_1_SDmaDescAddrMisalignErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaUnexpDataErr_LSB 0x2F
#define QIB_7322_ErrStatus_1_SDmaUnexpDataErr_MSB 0x2F
#define QIB_7322_ErrStatus_1_SDmaUnexpDataErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaMissingDwErr_LSB 0x2E
#define QIB_7322_ErrStatus_1_SDmaMissingDwErr_MSB 0x2E
#define QIB_7322_ErrStatus_1_SDmaMissingDwErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaDwEnErr_LSB 0x2D
#define QIB_7322_ErrStatus_1_SDmaDwEnErr_MSB 0x2D
#define QIB_7322_ErrStatus_1_SDmaDwEnErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaRpyTagErr_LSB 0x2C
#define QIB_7322_ErrStatus_1_SDmaRpyTagErr_MSB 0x2C
#define QIB_7322_ErrStatus_1_SDmaRpyTagErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDma1stDescErr_LSB 0x2B
#define QIB_7322_ErrStatus_1_SDma1stDescErr_MSB 0x2B
#define QIB_7322_ErrStatus_1_SDma1stDescErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaBaseErr_LSB 0x2A
#define QIB_7322_ErrStatus_1_SDmaBaseErr_MSB 0x2A
#define QIB_7322_ErrStatus_1_SDmaBaseErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaTailOutOfBoundErr_LSB 0x29
#define QIB_7322_ErrStatus_1_SDmaTailOutOfBoundErr_MSB 0x29
#define QIB_7322_ErrStatus_1_SDmaTailOutOfBoundErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaOutOfBoundErr_LSB 0x28
#define QIB_7322_ErrStatus_1_SDmaOutOfBoundErr_MSB 0x28
#define QIB_7322_ErrStatus_1_SDmaOutOfBoundErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SDmaGenMismatchErr_LSB 0x27
#define QIB_7322_ErrStatus_1_SDmaGenMismatchErr_MSB 0x27
#define QIB_7322_ErrStatus_1_SDmaGenMismatchErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendBufMisuseErr_LSB 0x26
#define QIB_7322_ErrStatus_1_SendBufMisuseErr_MSB 0x26
#define QIB_7322_ErrStatus_1_SendBufMisuseErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendUnsupportedVLErr_LSB 0x25
#define QIB_7322_ErrStatus_1_SendUnsupportedVLErr_MSB 0x25
#define QIB_7322_ErrStatus_1_SendUnsupportedVLErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendUnexpectedPktNumErr_LSB 0x24
#define QIB_7322_ErrStatus_1_SendUnexpectedPktNumErr_MSB 0x24
#define QIB_7322_ErrStatus_1_SendUnexpectedPktNumErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendDroppedDataPktErr_LSB 0x22
#define QIB_7322_ErrStatus_1_SendDroppedDataPktErr_MSB 0x22
#define QIB_7322_ErrStatus_1_SendDroppedDataPktErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendDroppedSmpPktErr_LSB 0x21
#define QIB_7322_ErrStatus_1_SendDroppedSmpPktErr_MSB 0x21
#define QIB_7322_ErrStatus_1_SendDroppedSmpPktErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendPktLenErr_LSB 0x20
#define QIB_7322_ErrStatus_1_SendPktLenErr_MSB 0x20
#define QIB_7322_ErrStatus_1_SendPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendUnderRunErr_LSB 0x1F
#define QIB_7322_ErrStatus_1_SendUnderRunErr_MSB 0x1F
#define QIB_7322_ErrStatus_1_SendUnderRunErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendMaxPktLenErr_LSB 0x1E
#define QIB_7322_ErrStatus_1_SendMaxPktLenErr_MSB 0x1E
#define QIB_7322_ErrStatus_1_SendMaxPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_SendMinPktLenErr_LSB 0x1D
#define QIB_7322_ErrStatus_1_SendMinPktLenErr_MSB 0x1D
#define QIB_7322_ErrStatus_1_SendMinPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvIBLostLinkErr_LSB 0x11
#define QIB_7322_ErrStatus_1_RcvIBLostLinkErr_MSB 0x11
#define QIB_7322_ErrStatus_1_RcvIBLostLinkErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvHdrErr_LSB 0x10
#define QIB_7322_ErrStatus_1_RcvHdrErr_MSB 0x10
#define QIB_7322_ErrStatus_1_RcvHdrErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvHdrLenErr_LSB 0xF
#define QIB_7322_ErrStatus_1_RcvHdrLenErr_MSB 0xF
#define QIB_7322_ErrStatus_1_RcvHdrLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvBadTidErr_LSB 0xE
#define QIB_7322_ErrStatus_1_RcvBadTidErr_MSB 0xE
#define QIB_7322_ErrStatus_1_RcvBadTidErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvBadVersionErr_LSB 0xB
#define QIB_7322_ErrStatus_1_RcvBadVersionErr_MSB 0xB
#define QIB_7322_ErrStatus_1_RcvBadVersionErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvIBFlowErr_LSB 0xA
#define QIB_7322_ErrStatus_1_RcvIBFlowErr_MSB 0xA
#define QIB_7322_ErrStatus_1_RcvIBFlowErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvEBPErr_LSB 0x9
#define QIB_7322_ErrStatus_1_RcvEBPErr_MSB 0x9
#define QIB_7322_ErrStatus_1_RcvEBPErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvUnsupportedVLErr_LSB 0x8
#define QIB_7322_ErrStatus_1_RcvUnsupportedVLErr_MSB 0x8
#define QIB_7322_ErrStatus_1_RcvUnsupportedVLErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvUnexpectedCharErr_LSB 0x7
#define QIB_7322_ErrStatus_1_RcvUnexpectedCharErr_MSB 0x7
#define QIB_7322_ErrStatus_1_RcvUnexpectedCharErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvShortPktLenErr_LSB 0x6
#define QIB_7322_ErrStatus_1_RcvShortPktLenErr_MSB 0x6
#define QIB_7322_ErrStatus_1_RcvShortPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvLongPktLenErr_LSB 0x5
#define QIB_7322_ErrStatus_1_RcvLongPktLenErr_MSB 0x5
#define QIB_7322_ErrStatus_1_RcvLongPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvMaxPktLenErr_LSB 0x4
#define QIB_7322_ErrStatus_1_RcvMaxPktLenErr_MSB 0x4
#define QIB_7322_ErrStatus_1_RcvMaxPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvMinPktLenErr_LSB 0x3
#define QIB_7322_ErrStatus_1_RcvMinPktLenErr_MSB 0x3
#define QIB_7322_ErrStatus_1_RcvMinPktLenErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvICRCErr_LSB 0x2
#define QIB_7322_ErrStatus_1_RcvICRCErr_MSB 0x2
#define QIB_7322_ErrStatus_1_RcvICRCErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvVCRCErr_LSB 0x1
#define QIB_7322_ErrStatus_1_RcvVCRCErr_MSB 0x1
#define QIB_7322_ErrStatus_1_RcvVCRCErr_RMASK 0x1
#define QIB_7322_ErrStatus_1_RcvFormatErr_LSB 0x0
#define QIB_7322_ErrStatus_1_RcvFormatErr_MSB 0x0
#define QIB_7322_ErrStatus_1_RcvFormatErr_RMASK 0x1

#define QIB_7322_ErrClear_1_OFFS 0x2090
#define QIB_7322_ErrClear_1_DEF 0x0000000000000000
#define QIB_7322_ErrClear_1_IBStatusChangedClear_LSB 0x3A
#define QIB_7322_ErrClear_1_IBStatusChangedClear_MSB 0x3A
#define QIB_7322_ErrClear_1_IBStatusChangedClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SHeadersErrClear_LSB 0x39
#define QIB_7322_ErrClear_1_SHeadersErrClear_MSB 0x39
#define QIB_7322_ErrClear_1_SHeadersErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_VL15BufMisuseErrClear_LSB 0x36
#define QIB_7322_ErrClear_1_VL15BufMisuseErrClear_MSB 0x36
#define QIB_7322_ErrClear_1_VL15BufMisuseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaHaltErrClear_LSB 0x31
#define QIB_7322_ErrClear_1_SDmaHaltErrClear_MSB 0x31
#define QIB_7322_ErrClear_1_SDmaHaltErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaDescAddrMisalignErrClear_LSB 0x30
#define QIB_7322_ErrClear_1_SDmaDescAddrMisalignErrClear_MSB 0x30
#define QIB_7322_ErrClear_1_SDmaDescAddrMisalignErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaUnexpDataErrClear_LSB 0x2F
#define QIB_7322_ErrClear_1_SDmaUnexpDataErrClear_MSB 0x2F
#define QIB_7322_ErrClear_1_SDmaUnexpDataErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaMissingDwErrClear_LSB 0x2E
#define QIB_7322_ErrClear_1_SDmaMissingDwErrClear_MSB 0x2E
#define QIB_7322_ErrClear_1_SDmaMissingDwErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaDwEnErrClear_LSB 0x2D
#define QIB_7322_ErrClear_1_SDmaDwEnErrClear_MSB 0x2D
#define QIB_7322_ErrClear_1_SDmaDwEnErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaRpyTagErrClear_LSB 0x2C
#define QIB_7322_ErrClear_1_SDmaRpyTagErrClear_MSB 0x2C
#define QIB_7322_ErrClear_1_SDmaRpyTagErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDma1stDescErrClear_LSB 0x2B
#define QIB_7322_ErrClear_1_SDma1stDescErrClear_MSB 0x2B
#define QIB_7322_ErrClear_1_SDma1stDescErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaBaseErrClear_LSB 0x2A
#define QIB_7322_ErrClear_1_SDmaBaseErrClear_MSB 0x2A
#define QIB_7322_ErrClear_1_SDmaBaseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaTailOutOfBoundErrClear_LSB 0x29
#define QIB_7322_ErrClear_1_SDmaTailOutOfBoundErrClear_MSB 0x29
#define QIB_7322_ErrClear_1_SDmaTailOutOfBoundErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaOutOfBoundErrClear_LSB 0x28
#define QIB_7322_ErrClear_1_SDmaOutOfBoundErrClear_MSB 0x28
#define QIB_7322_ErrClear_1_SDmaOutOfBoundErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SDmaGenMismatchErrClear_LSB 0x27
#define QIB_7322_ErrClear_1_SDmaGenMismatchErrClear_MSB 0x27
#define QIB_7322_ErrClear_1_SDmaGenMismatchErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendBufMisuseErrClear_LSB 0x26
#define QIB_7322_ErrClear_1_SendBufMisuseErrClear_MSB 0x26
#define QIB_7322_ErrClear_1_SendBufMisuseErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendUnsupportedVLErrClear_LSB 0x25
#define QIB_7322_ErrClear_1_SendUnsupportedVLErrClear_MSB 0x25
#define QIB_7322_ErrClear_1_SendUnsupportedVLErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendUnexpectedPktNumErrClear_LSB 0x24
#define QIB_7322_ErrClear_1_SendUnexpectedPktNumErrClear_MSB 0x24
#define QIB_7322_ErrClear_1_SendUnexpectedPktNumErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendDroppedDataPktErrClear_LSB 0x22
#define QIB_7322_ErrClear_1_SendDroppedDataPktErrClear_MSB 0x22
#define QIB_7322_ErrClear_1_SendDroppedDataPktErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendDroppedSmpPktErrClear_LSB 0x21
#define QIB_7322_ErrClear_1_SendDroppedSmpPktErrClear_MSB 0x21
#define QIB_7322_ErrClear_1_SendDroppedSmpPktErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendPktLenErrClear_LSB 0x20
#define QIB_7322_ErrClear_1_SendPktLenErrClear_MSB 0x20
#define QIB_7322_ErrClear_1_SendPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendUnderRunErrClear_LSB 0x1F
#define QIB_7322_ErrClear_1_SendUnderRunErrClear_MSB 0x1F
#define QIB_7322_ErrClear_1_SendUnderRunErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendMaxPktLenErrClear_LSB 0x1E
#define QIB_7322_ErrClear_1_SendMaxPktLenErrClear_MSB 0x1E
#define QIB_7322_ErrClear_1_SendMaxPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_SendMinPktLenErrClear_LSB 0x1D
#define QIB_7322_ErrClear_1_SendMinPktLenErrClear_MSB 0x1D
#define QIB_7322_ErrClear_1_SendMinPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvIBLostLinkErrClear_LSB 0x11
#define QIB_7322_ErrClear_1_RcvIBLostLinkErrClear_MSB 0x11
#define QIB_7322_ErrClear_1_RcvIBLostLinkErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvHdrErrClear_LSB 0x10
#define QIB_7322_ErrClear_1_RcvHdrErrClear_MSB 0x10
#define QIB_7322_ErrClear_1_RcvHdrErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvHdrLenErrClear_LSB 0xF
#define QIB_7322_ErrClear_1_RcvHdrLenErrClear_MSB 0xF
#define QIB_7322_ErrClear_1_RcvHdrLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvBadTidErrClear_LSB 0xE
#define QIB_7322_ErrClear_1_RcvBadTidErrClear_MSB 0xE
#define QIB_7322_ErrClear_1_RcvBadTidErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvBadVersionErrClear_LSB 0xB
#define QIB_7322_ErrClear_1_RcvBadVersionErrClear_MSB 0xB
#define QIB_7322_ErrClear_1_RcvBadVersionErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvIBFlowErrClear_LSB 0xA
#define QIB_7322_ErrClear_1_RcvIBFlowErrClear_MSB 0xA
#define QIB_7322_ErrClear_1_RcvIBFlowErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvEBPErrClear_LSB 0x9
#define QIB_7322_ErrClear_1_RcvEBPErrClear_MSB 0x9
#define QIB_7322_ErrClear_1_RcvEBPErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvUnsupportedVLErrClear_LSB 0x8
#define QIB_7322_ErrClear_1_RcvUnsupportedVLErrClear_MSB 0x8
#define QIB_7322_ErrClear_1_RcvUnsupportedVLErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvUnexpectedCharErrClear_LSB 0x7
#define QIB_7322_ErrClear_1_RcvUnexpectedCharErrClear_MSB 0x7
#define QIB_7322_ErrClear_1_RcvUnexpectedCharErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvShortPktLenErrClear_LSB 0x6
#define QIB_7322_ErrClear_1_RcvShortPktLenErrClear_MSB 0x6
#define QIB_7322_ErrClear_1_RcvShortPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvLongPktLenErrClear_LSB 0x5
#define QIB_7322_ErrClear_1_RcvLongPktLenErrClear_MSB 0x5
#define QIB_7322_ErrClear_1_RcvLongPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvMaxPktLenErrClear_LSB 0x4
#define QIB_7322_ErrClear_1_RcvMaxPktLenErrClear_MSB 0x4
#define QIB_7322_ErrClear_1_RcvMaxPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvMinPktLenErrClear_LSB 0x3
#define QIB_7322_ErrClear_1_RcvMinPktLenErrClear_MSB 0x3
#define QIB_7322_ErrClear_1_RcvMinPktLenErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvICRCErrClear_LSB 0x2
#define QIB_7322_ErrClear_1_RcvICRCErrClear_MSB 0x2
#define QIB_7322_ErrClear_1_RcvICRCErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvVCRCErrClear_LSB 0x1
#define QIB_7322_ErrClear_1_RcvVCRCErrClear_MSB 0x1
#define QIB_7322_ErrClear_1_RcvVCRCErrClear_RMASK 0x1
#define QIB_7322_ErrClear_1_RcvFormatErrClear_LSB 0x0
#define QIB_7322_ErrClear_1_RcvFormatErrClear_MSB 0x0
#define QIB_7322_ErrClear_1_RcvFormatErrClear_RMASK 0x1

#define QIB_7322_TXEStatus_1_OFFS 0x20B8
#define QIB_7322_TXEStatus_1_DEF 0x0000000XC00080FF
#define QIB_7322_TXEStatus_1_TXE_IBC_Idle_LSB 0x1F
#define QIB_7322_TXEStatus_1_TXE_IBC_Idle_MSB 0x1F
#define QIB_7322_TXEStatus_1_TXE_IBC_Idle_RMASK 0x1
#define QIB_7322_TXEStatus_1_RmFifoEmpty_LSB 0x1E
#define QIB_7322_TXEStatus_1_RmFifoEmpty_MSB 0x1E
#define QIB_7322_TXEStatus_1_RmFifoEmpty_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL15_LSB 0xF
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL15_MSB 0xF
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL15_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL7_LSB 0x7
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL7_MSB 0x7
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL7_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL6_LSB 0x6
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL6_MSB 0x6
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL6_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL5_LSB 0x5
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL5_MSB 0x5
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL5_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL4_LSB 0x4
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL4_MSB 0x4
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL4_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL3_LSB 0x3
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL3_MSB 0x3
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL3_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL2_LSB 0x2
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL2_MSB 0x2
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL2_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL1_LSB 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL1_MSB 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL1_RMASK 0x1
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL0_LSB 0x0
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL0_MSB 0x0
#define QIB_7322_TXEStatus_1_LaFifoEmpty_VL0_RMASK 0x1

#define QIB_7322_RcvCtrl_1_OFFS 0x2100
#define QIB_7322_RcvCtrl_1_DEF 0x0000000000000000
#define QIB_7322_RcvCtrl_1_RcvResetCredit_LSB 0x2A
#define QIB_7322_RcvCtrl_1_RcvResetCredit_MSB 0x2A
#define QIB_7322_RcvCtrl_1_RcvResetCredit_RMASK 0x1
#define QIB_7322_RcvCtrl_1_RcvPartitionKeyDisable_LSB 0x29
#define QIB_7322_RcvCtrl_1_RcvPartitionKeyDisable_MSB 0x29
#define QIB_7322_RcvCtrl_1_RcvPartitionKeyDisable_RMASK 0x1
#define QIB_7322_RcvCtrl_1_RcvQPMapEnable_LSB 0x28
#define QIB_7322_RcvCtrl_1_RcvQPMapEnable_MSB 0x28
#define QIB_7322_RcvCtrl_1_RcvQPMapEnable_RMASK 0x1
#define QIB_7322_RcvCtrl_1_RcvIBPortEnable_LSB 0x27
#define QIB_7322_RcvCtrl_1_RcvIBPortEnable_MSB 0x27
#define QIB_7322_RcvCtrl_1_RcvIBPortEnable_RMASK 0x1
#define QIB_7322_RcvCtrl_1_ContextEnableUser_LSB 0x2
#define QIB_7322_RcvCtrl_1_ContextEnableUser_MSB 0x11
#define QIB_7322_RcvCtrl_1_ContextEnableUser_RMASK 0xFFFF
#define QIB_7322_RcvCtrl_1_ContextEnableKernel_LSB 0x1
#define QIB_7322_RcvCtrl_1_ContextEnableKernel_MSB 0x1
#define QIB_7322_RcvCtrl_1_ContextEnableKernel_RMASK 0x1

#define QIB_7322_RcvBTHQP_1_OFFS 0x2108
#define QIB_7322_RcvBTHQP_1_DEF 0x0000000000000000
#define QIB_7322_RcvBTHQP_1_RcvBTHQP_LSB 0x0
#define QIB_7322_RcvBTHQP_1_RcvBTHQP_MSB 0x17
#define QIB_7322_RcvBTHQP_1_RcvBTHQP_RMASK 0xFFFFFF

#define QIB_7322_RcvQPMapTableA_1_OFFS 0x2110
#define QIB_7322_RcvQPMapTableA_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext5_LSB 0x19
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext5_MSB 0x1D
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext5_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext4_LSB 0x14
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext4_MSB 0x18
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext4_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext3_LSB 0xF
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext3_MSB 0x13
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext3_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext2_LSB 0xA
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext2_MSB 0xE
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext2_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext1_LSB 0x5
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext1_MSB 0x9
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext1_RMASK 0x1F
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext0_LSB 0x0
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext0_MSB 0x4
#define QIB_7322_RcvQPMapTableA_1_RcvQPMapContext0_RMASK 0x1F

#define QIB_7322_RcvQPMapTableB_1_OFFS 0x2118
#define QIB_7322_RcvQPMapTableB_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext11_LSB 0x19
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext11_MSB 0x1D
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext11_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext10_LSB 0x14
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext10_MSB 0x18
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext10_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext9_LSB 0xF
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext9_MSB 0x13
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext9_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext8_LSB 0xA
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext8_MSB 0xE
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext8_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext7_LSB 0x5
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext7_MSB 0x9
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext7_RMASK 0x1F
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext6_LSB 0x0
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext6_MSB 0x4
#define QIB_7322_RcvQPMapTableB_1_RcvQPMapContext6_RMASK 0x1F

#define QIB_7322_RcvQPMapTableC_1_OFFS 0x2120
#define QIB_7322_RcvQPMapTableC_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext17_LSB 0x19
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext17_MSB 0x1D
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext17_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext16_LSB 0x14
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext16_MSB 0x18
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext16_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext15_LSB 0xF
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext15_MSB 0x13
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext15_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext14_LSB 0xA
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext14_MSB 0xE
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext14_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext13_LSB 0x5
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext13_MSB 0x9
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext13_RMASK 0x1F
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext12_LSB 0x0
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext12_MSB 0x4
#define QIB_7322_RcvQPMapTableC_1_RcvQPMapContext12_RMASK 0x1F

#define QIB_7322_RcvQPMapTableD_1_OFFS 0x2128
#define QIB_7322_RcvQPMapTableD_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext23_LSB 0x19
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext23_MSB 0x1D
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext23_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext22_LSB 0x14
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext22_MSB 0x18
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext22_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext21_LSB 0xF
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext21_MSB 0x13
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext21_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext20_LSB 0xA
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext20_MSB 0xE
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext20_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext19_LSB 0x5
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext19_MSB 0x9
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext19_RMASK 0x1F
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext18_LSB 0x0
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext18_MSB 0x4
#define QIB_7322_RcvQPMapTableD_1_RcvQPMapContext18_RMASK 0x1F

#define QIB_7322_RcvQPMapTableE_1_OFFS 0x2130
#define QIB_7322_RcvQPMapTableE_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext29_LSB 0x19
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext29_MSB 0x1D
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext29_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext28_LSB 0x14
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext28_MSB 0x18
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext28_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext27_LSB 0xF
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext27_MSB 0x13
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext27_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext26_LSB 0xA
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext26_MSB 0xE
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext26_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext25_LSB 0x5
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext25_MSB 0x9
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext25_RMASK 0x1F
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext24_LSB 0x0
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext24_MSB 0x4
#define QIB_7322_RcvQPMapTableE_1_RcvQPMapContext24_RMASK 0x1F

#define QIB_7322_RcvQPMapTableF_1_OFFS 0x2138
#define QIB_7322_RcvQPMapTableF_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMapTableF_1_RcvQPMapContext31_LSB 0x5
#define QIB_7322_RcvQPMapTableF_1_RcvQPMapContext31_MSB 0x9
#define QIB_7322_RcvQPMapTableF_1_RcvQPMapContext31_RMASK 0x1F
#define QIB_7322_RcvQPMapTableF_1_RcvQPMapContext30_LSB 0x0
#define QIB_7322_RcvQPMapTableF_1_RcvQPMapContext30_MSB 0x4
#define QIB_7322_RcvQPMapTableF_1_RcvQPMapContext30_RMASK 0x1F

#define QIB_7322_PSStat_1_OFFS 0x2140
#define QIB_7322_PSStat_1_DEF 0x0000000000000000

#define QIB_7322_PSStart_1_OFFS 0x2148
#define QIB_7322_PSStart_1_DEF 0x0000000000000000

#define QIB_7322_PSInterval_1_OFFS 0x2150
#define QIB_7322_PSInterval_1_DEF 0x0000000000000000

#define QIB_7322_RcvStatus_1_OFFS 0x2160
#define QIB_7322_RcvStatus_1_DEF 0x0000000000000000
#define QIB_7322_RcvStatus_1_DmaeqBlockingContext_LSB 0x1
#define QIB_7322_RcvStatus_1_DmaeqBlockingContext_MSB 0x5
#define QIB_7322_RcvStatus_1_DmaeqBlockingContext_RMASK 0x1F
#define QIB_7322_RcvStatus_1_RxPktInProgress_LSB 0x0
#define QIB_7322_RcvStatus_1_RxPktInProgress_MSB 0x0
#define QIB_7322_RcvStatus_1_RxPktInProgress_RMASK 0x1

#define QIB_7322_RcvPartitionKey_1_OFFS 0x2168
#define QIB_7322_RcvPartitionKey_1_DEF 0x0000000000000000

#define QIB_7322_RcvQPMulticastContext_1_OFFS 0x2170
#define QIB_7322_RcvQPMulticastContext_1_DEF 0x0000000000000000
#define QIB_7322_RcvQPMulticastContext_1_RcvQpMcContext_LSB 0x0
#define QIB_7322_RcvQPMulticastContext_1_RcvQpMcContext_MSB 0x4
#define QIB_7322_RcvQPMulticastContext_1_RcvQpMcContext_RMASK 0x1F

#define QIB_7322_RcvPktLEDCnt_1_OFFS 0x2178
#define QIB_7322_RcvPktLEDCnt_1_DEF 0x0000000000000000
#define QIB_7322_RcvPktLEDCnt_1_ONperiod_LSB 0x20
#define QIB_7322_RcvPktLEDCnt_1_ONperiod_MSB 0x3F
#define QIB_7322_RcvPktLEDCnt_1_ONperiod_RMASK 0xFFFFFFFF
#define QIB_7322_RcvPktLEDCnt_1_OFFperiod_LSB 0x0
#define QIB_7322_RcvPktLEDCnt_1_OFFperiod_MSB 0x1F
#define QIB_7322_RcvPktLEDCnt_1_OFFperiod_RMASK 0xFFFFFFFF

#define QIB_7322_SendDmaIdleCnt_1_OFFS 0x2180
#define QIB_7322_SendDmaIdleCnt_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaIdleCnt_1_SendDmaIdleCnt_LSB 0x0
#define QIB_7322_SendDmaIdleCnt_1_SendDmaIdleCnt_MSB 0xF
#define QIB_7322_SendDmaIdleCnt_1_SendDmaIdleCnt_RMASK 0xFFFF

#define QIB_7322_SendDmaReloadCnt_1_OFFS 0x2188
#define QIB_7322_SendDmaReloadCnt_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaReloadCnt_1_SendDmaReloadCnt_LSB 0x0
#define QIB_7322_SendDmaReloadCnt_1_SendDmaReloadCnt_MSB 0xF
#define QIB_7322_SendDmaReloadCnt_1_SendDmaReloadCnt_RMASK 0xFFFF

#define QIB_7322_SendDmaDescCnt_1_OFFS 0x2190
#define QIB_7322_SendDmaDescCnt_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaDescCnt_1_SendDmaDescCnt_LSB 0x0
#define QIB_7322_SendDmaDescCnt_1_SendDmaDescCnt_MSB 0xF
#define QIB_7322_SendDmaDescCnt_1_SendDmaDescCnt_RMASK 0xFFFF

#define QIB_7322_SendCtrl_1_OFFS 0x21C0
#define QIB_7322_SendCtrl_1_DEF 0x0000000000000000
#define QIB_7322_SendCtrl_1_IBVLArbiterEn_LSB 0xF
#define QIB_7322_SendCtrl_1_IBVLArbiterEn_MSB 0xF
#define QIB_7322_SendCtrl_1_IBVLArbiterEn_RMASK 0x1
#define QIB_7322_SendCtrl_1_TxeDrainRmFifo_LSB 0xE
#define QIB_7322_SendCtrl_1_TxeDrainRmFifo_MSB 0xE
#define QIB_7322_SendCtrl_1_TxeDrainRmFifo_RMASK 0x1
#define QIB_7322_SendCtrl_1_TxeDrainLaFifo_LSB 0xD
#define QIB_7322_SendCtrl_1_TxeDrainLaFifo_MSB 0xD
#define QIB_7322_SendCtrl_1_TxeDrainLaFifo_RMASK 0x1
#define QIB_7322_SendCtrl_1_SDmaHalt_LSB 0xC
#define QIB_7322_SendCtrl_1_SDmaHalt_MSB 0xC
#define QIB_7322_SendCtrl_1_SDmaHalt_RMASK 0x1
#define QIB_7322_SendCtrl_1_SDmaEnable_LSB 0xB
#define QIB_7322_SendCtrl_1_SDmaEnable_MSB 0xB
#define QIB_7322_SendCtrl_1_SDmaEnable_RMASK 0x1
#define QIB_7322_SendCtrl_1_SDmaSingleDescriptor_LSB 0xA
#define QIB_7322_SendCtrl_1_SDmaSingleDescriptor_MSB 0xA
#define QIB_7322_SendCtrl_1_SDmaSingleDescriptor_RMASK 0x1
#define QIB_7322_SendCtrl_1_SDmaIntEnable_LSB 0x9
#define QIB_7322_SendCtrl_1_SDmaIntEnable_MSB 0x9
#define QIB_7322_SendCtrl_1_SDmaIntEnable_RMASK 0x1
#define QIB_7322_SendCtrl_1_SDmaCleanup_LSB 0x8
#define QIB_7322_SendCtrl_1_SDmaCleanup_MSB 0x8
#define QIB_7322_SendCtrl_1_SDmaCleanup_RMASK 0x1
#define QIB_7322_SendCtrl_1_ForceCreditUpToDate_LSB 0x7
#define QIB_7322_SendCtrl_1_ForceCreditUpToDate_MSB 0x7
#define QIB_7322_SendCtrl_1_ForceCreditUpToDate_RMASK 0x1
#define QIB_7322_SendCtrl_1_SendEnable_LSB 0x3
#define QIB_7322_SendCtrl_1_SendEnable_MSB 0x3
#define QIB_7322_SendCtrl_1_SendEnable_RMASK 0x1
#define QIB_7322_SendCtrl_1_TxeBypassIbc_LSB 0x1
#define QIB_7322_SendCtrl_1_TxeBypassIbc_MSB 0x1
#define QIB_7322_SendCtrl_1_TxeBypassIbc_RMASK 0x1
#define QIB_7322_SendCtrl_1_TxeAbortIbc_LSB 0x0
#define QIB_7322_SendCtrl_1_TxeAbortIbc_MSB 0x0
#define QIB_7322_SendCtrl_1_TxeAbortIbc_RMASK 0x1

#define QIB_7322_SendDmaBase_1_OFFS 0x21F8
#define QIB_7322_SendDmaBase_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaBase_1_SendDmaBase_LSB 0x0
#define QIB_7322_SendDmaBase_1_SendDmaBase_MSB 0x2F
#define QIB_7322_SendDmaBase_1_SendDmaBase_RMASK 0xFFFFFFFFFFFF

#define QIB_7322_SendDmaLenGen_1_OFFS 0x2200
#define QIB_7322_SendDmaLenGen_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaLenGen_1_Generation_LSB 0x10
#define QIB_7322_SendDmaLenGen_1_Generation_MSB 0x12
#define QIB_7322_SendDmaLenGen_1_Generation_RMASK 0x7
#define QIB_7322_SendDmaLenGen_1_Length_LSB 0x0
#define QIB_7322_SendDmaLenGen_1_Length_MSB 0xF
#define QIB_7322_SendDmaLenGen_1_Length_RMASK 0xFFFF

#define QIB_7322_SendDmaTail_1_OFFS 0x2208
#define QIB_7322_SendDmaTail_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaTail_1_SendDmaTail_LSB 0x0
#define QIB_7322_SendDmaTail_1_SendDmaTail_MSB 0xF
#define QIB_7322_SendDmaTail_1_SendDmaTail_RMASK 0xFFFF

#define QIB_7322_SendDmaHead_1_OFFS 0x2210
#define QIB_7322_SendDmaHead_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaHead_1_InternalSendDmaHead_LSB 0x20
#define QIB_7322_SendDmaHead_1_InternalSendDmaHead_MSB 0x2F
#define QIB_7322_SendDmaHead_1_InternalSendDmaHead_RMASK 0xFFFF
#define QIB_7322_SendDmaHead_1_SendDmaHead_LSB 0x0
#define QIB_7322_SendDmaHead_1_SendDmaHead_MSB 0xF
#define QIB_7322_SendDmaHead_1_SendDmaHead_RMASK 0xFFFF

#define QIB_7322_SendDmaHeadAddr_1_OFFS 0x2218
#define QIB_7322_SendDmaHeadAddr_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaHeadAddr_1_SendDmaHeadAddr_LSB 0x0
#define QIB_7322_SendDmaHeadAddr_1_SendDmaHeadAddr_MSB 0x2F
#define QIB_7322_SendDmaHeadAddr_1_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF

#define QIB_7322_SendDmaBufMask0_1_OFFS 0x2220
#define QIB_7322_SendDmaBufMask0_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaBufMask0_1_BufMask_63_0_LSB 0x0
#define QIB_7322_SendDmaBufMask0_1_BufMask_63_0_MSB 0x3F
#define QIB_7322_SendDmaBufMask0_1_BufMask_63_0_RMASK 0x0

#define QIB_7322_SendDmaStatus_1_OFFS 0x2238
#define QIB_7322_SendDmaStatus_1_DEF 0x0000000042000000
#define QIB_7322_SendDmaStatus_1_ScoreBoardDrainInProg_LSB 0x3F
#define QIB_7322_SendDmaStatus_1_ScoreBoardDrainInProg_MSB 0x3F
#define QIB_7322_SendDmaStatus_1_ScoreBoardDrainInProg_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_HaltInProg_LSB 0x3E
#define QIB_7322_SendDmaStatus_1_HaltInProg_MSB 0x3E
#define QIB_7322_SendDmaStatus_1_HaltInProg_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_InternalSDmaHalt_LSB 0x3D
#define QIB_7322_SendDmaStatus_1_InternalSDmaHalt_MSB 0x3D
#define QIB_7322_SendDmaStatus_1_InternalSDmaHalt_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_ScbDescIndex_13_0_LSB 0x2F
#define QIB_7322_SendDmaStatus_1_ScbDescIndex_13_0_MSB 0x3C
#define QIB_7322_SendDmaStatus_1_ScbDescIndex_13_0_RMASK 0x3FFF
#define QIB_7322_SendDmaStatus_1_RpyLowAddr_6_0_LSB 0x28
#define QIB_7322_SendDmaStatus_1_RpyLowAddr_6_0_MSB 0x2E
#define QIB_7322_SendDmaStatus_1_RpyLowAddr_6_0_RMASK 0x7F
#define QIB_7322_SendDmaStatus_1_RpyTag_7_0_LSB 0x20
#define QIB_7322_SendDmaStatus_1_RpyTag_7_0_MSB 0x27
#define QIB_7322_SendDmaStatus_1_RpyTag_7_0_RMASK 0xFF
#define QIB_7322_SendDmaStatus_1_ScbFull_LSB 0x1F
#define QIB_7322_SendDmaStatus_1_ScbFull_MSB 0x1F
#define QIB_7322_SendDmaStatus_1_ScbFull_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_ScbEmpty_LSB 0x1E
#define QIB_7322_SendDmaStatus_1_ScbEmpty_MSB 0x1E
#define QIB_7322_SendDmaStatus_1_ScbEmpty_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_ScbEntryValid_LSB 0x1D
#define QIB_7322_SendDmaStatus_1_ScbEntryValid_MSB 0x1D
#define QIB_7322_SendDmaStatus_1_ScbEntryValid_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_ScbFetchDescFlag_LSB 0x1C
#define QIB_7322_SendDmaStatus_1_ScbFetchDescFlag_MSB 0x1C
#define QIB_7322_SendDmaStatus_1_ScbFetchDescFlag_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_SplFifoReadyToGo_LSB 0x1B
#define QIB_7322_SendDmaStatus_1_SplFifoReadyToGo_MSB 0x1B
#define QIB_7322_SendDmaStatus_1_SplFifoReadyToGo_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_SplFifoDisarmed_LSB 0x1A
#define QIB_7322_SendDmaStatus_1_SplFifoDisarmed_MSB 0x1A
#define QIB_7322_SendDmaStatus_1_SplFifoDisarmed_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_SplFifoEmpty_LSB 0x19
#define QIB_7322_SendDmaStatus_1_SplFifoEmpty_MSB 0x19
#define QIB_7322_SendDmaStatus_1_SplFifoEmpty_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_SplFifoFull_LSB 0x18
#define QIB_7322_SendDmaStatus_1_SplFifoFull_MSB 0x18
#define QIB_7322_SendDmaStatus_1_SplFifoFull_RMASK 0x1
#define QIB_7322_SendDmaStatus_1_SplFifoBufNum_LSB 0x10
#define QIB_7322_SendDmaStatus_1_SplFifoBufNum_MSB 0x17
#define QIB_7322_SendDmaStatus_1_SplFifoBufNum_RMASK 0xFF
#define QIB_7322_SendDmaStatus_1_SplFifoDescIndex_LSB 0x0
#define QIB_7322_SendDmaStatus_1_SplFifoDescIndex_MSB 0xF
#define QIB_7322_SendDmaStatus_1_SplFifoDescIndex_RMASK 0xFFFF

#define QIB_7322_SendDmaPriorityThld_1_OFFS 0x2258
#define QIB_7322_SendDmaPriorityThld_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaPriorityThld_1_PriorityThreshold_LSB 0x0
#define QIB_7322_SendDmaPriorityThld_1_PriorityThreshold_MSB 0x3
#define QIB_7322_SendDmaPriorityThld_1_PriorityThreshold_RMASK 0xF

#define QIB_7322_SendHdrErrSymptom_1_OFFS 0x2260
#define QIB_7322_SendHdrErrSymptom_1_DEF 0x0000000000000000
#define QIB_7322_SendHdrErrSymptom_1_NonKeyPacket_LSB 0x6
#define QIB_7322_SendHdrErrSymptom_1_NonKeyPacket_MSB 0x6
#define QIB_7322_SendHdrErrSymptom_1_NonKeyPacket_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_1_GRHFail_LSB 0x5
#define QIB_7322_SendHdrErrSymptom_1_GRHFail_MSB 0x5
#define QIB_7322_SendHdrErrSymptom_1_GRHFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_1_PkeyFail_LSB 0x4
#define QIB_7322_SendHdrErrSymptom_1_PkeyFail_MSB 0x4
#define QIB_7322_SendHdrErrSymptom_1_PkeyFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_1_QPFail_LSB 0x3
#define QIB_7322_SendHdrErrSymptom_1_QPFail_MSB 0x3
#define QIB_7322_SendHdrErrSymptom_1_QPFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_1_SLIDFail_LSB 0x2
#define QIB_7322_SendHdrErrSymptom_1_SLIDFail_MSB 0x2
#define QIB_7322_SendHdrErrSymptom_1_SLIDFail_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_1_RawIPV6_LSB 0x1
#define QIB_7322_SendHdrErrSymptom_1_RawIPV6_MSB 0x1
#define QIB_7322_SendHdrErrSymptom_1_RawIPV6_RMASK 0x1
#define QIB_7322_SendHdrErrSymptom_1_PacketTooSmall_LSB 0x0
#define QIB_7322_SendHdrErrSymptom_1_PacketTooSmall_MSB 0x0
#define QIB_7322_SendHdrErrSymptom_1_PacketTooSmall_RMASK 0x1

#define QIB_7322_RxCreditVL0_1_OFFS 0x2280
#define QIB_7322_RxCreditVL0_1_DEF 0x0000000000000000
#define QIB_7322_RxCreditVL0_1_RxBufrConsumedVL_LSB 0x10
#define QIB_7322_RxCreditVL0_1_RxBufrConsumedVL_MSB 0x1B
#define QIB_7322_RxCreditVL0_1_RxBufrConsumedVL_RMASK 0xFFF
#define QIB_7322_RxCreditVL0_1_RxMaxCreditVL_LSB 0x0
#define QIB_7322_RxCreditVL0_1_RxMaxCreditVL_MSB 0xB
#define QIB_7322_RxCreditVL0_1_RxMaxCreditVL_RMASK 0xFFF

#define QIB_7322_SendDmaBufUsed0_1_OFFS 0x2480
#define QIB_7322_SendDmaBufUsed0_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaBufUsed0_1_BufUsed_63_0_LSB 0x0
#define QIB_7322_SendDmaBufUsed0_1_BufUsed_63_0_MSB 0x3F
#define QIB_7322_SendDmaBufUsed0_1_BufUsed_63_0_RMASK 0x0

#define QIB_7322_SendDmaReqTagUsed_1_OFFS 0x2498
#define QIB_7322_SendDmaReqTagUsed_1_DEF 0x0000000000000000
#define QIB_7322_SendDmaReqTagUsed_1_ReqTagUsed_7_0_LSB 0x0
#define QIB_7322_SendDmaReqTagUsed_1_ReqTagUsed_7_0_MSB 0x7
#define QIB_7322_SendDmaReqTagUsed_1_ReqTagUsed_7_0_RMASK 0xFF

#define QIB_7322_SendCheckControl_1_OFFS 0x24A8
#define QIB_7322_SendCheckControl_1_DEF 0x0000000000000000
#define QIB_7322_SendCheckControl_1_PKey_En_LSB 0x4
#define QIB_7322_SendCheckControl_1_PKey_En_MSB 0x4
#define QIB_7322_SendCheckControl_1_PKey_En_RMASK 0x1
#define QIB_7322_SendCheckControl_1_BTHQP_En_LSB 0x3
#define QIB_7322_SendCheckControl_1_BTHQP_En_MSB 0x3
#define QIB_7322_SendCheckControl_1_BTHQP_En_RMASK 0x1
#define QIB_7322_SendCheckControl_1_SLID_En_LSB 0x2
#define QIB_7322_SendCheckControl_1_SLID_En_MSB 0x2
#define QIB_7322_SendCheckControl_1_SLID_En_RMASK 0x1
#define QIB_7322_SendCheckControl_1_RawIPV6_En_LSB 0x1
#define QIB_7322_SendCheckControl_1_RawIPV6_En_MSB 0x1
#define QIB_7322_SendCheckControl_1_RawIPV6_En_RMASK 0x1
#define QIB_7322_SendCheckControl_1_PacketTooSmall_En_LSB 0x0
#define QIB_7322_SendCheckControl_1_PacketTooSmall_En_MSB 0x0
#define QIB_7322_SendCheckControl_1_PacketTooSmall_En_RMASK 0x1

#define QIB_7322_SendIBSLIDMask_1_OFFS 0x24B0
#define QIB_7322_SendIBSLIDMask_1_DEF 0x0000000000000000
#define QIB_7322_SendIBSLIDMask_1_SendIBSLIDMask_15_0_LSB 0x0
#define QIB_7322_SendIBSLIDMask_1_SendIBSLIDMask_15_0_MSB 0xF
#define QIB_7322_SendIBSLIDMask_1_SendIBSLIDMask_15_0_RMASK 0xFFFF

#define QIB_7322_SendIBSLIDAssign_1_OFFS 0x24B8
#define QIB_7322_SendIBSLIDAssign_1_DEF 0x0000000000000000
#define QIB_7322_SendIBSLIDAssign_1_SendIBSLIDAssign_15_0_LSB 0x0
#define QIB_7322_SendIBSLIDAssign_1_SendIBSLIDAssign_15_0_MSB 0xF
#define QIB_7322_SendIBSLIDAssign_1_SendIBSLIDAssign_15_0_RMASK 0xFFFF

#define QIB_7322_IBCStatusA_1_OFFS 0x2540
#define QIB_7322_IBCStatusA_1_DEF 0x0000000000000X02
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL7_LSB 0x27
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL7_MSB 0x27
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL7_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL6_LSB 0x26
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL6_MSB 0x26
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL6_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL5_LSB 0x25
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL5_MSB 0x25
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL5_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL4_LSB 0x24
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL4_MSB 0x24
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL4_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL3_LSB 0x23
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL3_MSB 0x23
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL3_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL2_LSB 0x22
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL2_MSB 0x22
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL2_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL1_LSB 0x21
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL1_MSB 0x21
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL1_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL0_LSB 0x20
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL0_MSB 0x20
#define QIB_7322_IBCStatusA_1_TxCreditOk_VL0_RMASK 0x1
#define QIB_7322_IBCStatusA_1_TxReady_LSB 0x1E
#define QIB_7322_IBCStatusA_1_TxReady_MSB 0x1E
#define QIB_7322_IBCStatusA_1_TxReady_RMASK 0x1
#define QIB_7322_IBCStatusA_1_LinkSpeedQDR_LSB 0x1D
#define QIB_7322_IBCStatusA_1_LinkSpeedQDR_MSB 0x1D
#define QIB_7322_IBCStatusA_1_LinkSpeedQDR_RMASK 0x1
#define QIB_7322_IBCStatusA_1_ScrambleCapRemote_LSB 0xF
#define QIB_7322_IBCStatusA_1_ScrambleCapRemote_MSB 0xF
#define QIB_7322_IBCStatusA_1_ScrambleCapRemote_RMASK 0x1
#define QIB_7322_IBCStatusA_1_ScrambleEn_LSB 0xE
#define QIB_7322_IBCStatusA_1_ScrambleEn_MSB 0xE
#define QIB_7322_IBCStatusA_1_ScrambleEn_RMASK 0x1
#define QIB_7322_IBCStatusA_1_IBTxLaneReversed_LSB 0xD
#define QIB_7322_IBCStatusA_1_IBTxLaneReversed_MSB 0xD
#define QIB_7322_IBCStatusA_1_IBTxLaneReversed_RMASK 0x1
#define QIB_7322_IBCStatusA_1_IBRxLaneReversed_LSB 0xC
#define QIB_7322_IBCStatusA_1_IBRxLaneReversed_MSB 0xC
#define QIB_7322_IBCStatusA_1_IBRxLaneReversed_RMASK 0x1
#define QIB_7322_IBCStatusA_1_DDS_RXEQ_FAIL_LSB 0xA
#define QIB_7322_IBCStatusA_1_DDS_RXEQ_FAIL_MSB 0xA
#define QIB_7322_IBCStatusA_1_DDS_RXEQ_FAIL_RMASK 0x1
#define QIB_7322_IBCStatusA_1_LinkWidthActive_LSB 0x9
#define QIB_7322_IBCStatusA_1_LinkWidthActive_MSB 0x9
#define QIB_7322_IBCStatusA_1_LinkWidthActive_RMASK 0x1
#define QIB_7322_IBCStatusA_1_LinkSpeedActive_LSB 0x8
#define QIB_7322_IBCStatusA_1_LinkSpeedActive_MSB 0x8
#define QIB_7322_IBCStatusA_1_LinkSpeedActive_RMASK 0x1
#define QIB_7322_IBCStatusA_1_LinkState_LSB 0x5
#define QIB_7322_IBCStatusA_1_LinkState_MSB 0x7
#define QIB_7322_IBCStatusA_1_LinkState_RMASK 0x7
#define QIB_7322_IBCStatusA_1_LinkTrainingState_LSB 0x0
#define QIB_7322_IBCStatusA_1_LinkTrainingState_MSB 0x4
#define QIB_7322_IBCStatusA_1_LinkTrainingState_RMASK 0x1F

#define QIB_7322_IBCStatusB_1_OFFS 0x2548
#define QIB_7322_IBCStatusB_1_DEF 0x00000000XXXXXXXX
#define QIB_7322_IBCStatusB_1_heartbeat_timed_out_LSB 0x24
#define QIB_7322_IBCStatusB_1_heartbeat_timed_out_MSB 0x24
#define QIB_7322_IBCStatusB_1_heartbeat_timed_out_RMASK 0x1
#define QIB_7322_IBCStatusB_1_heartbeat_crosstalk_LSB 0x20
#define QIB_7322_IBCStatusB_1_heartbeat_crosstalk_MSB 0x23
#define QIB_7322_IBCStatusB_1_heartbeat_crosstalk_RMASK 0xF
#define QIB_7322_IBCStatusB_1_RxEqLocalDevice_LSB 0x1E
#define QIB_7322_IBCStatusB_1_RxEqLocalDevice_MSB 0x1F
#define QIB_7322_IBCStatusB_1_RxEqLocalDevice_RMASK 0x3
#define QIB_7322_IBCStatusB_1_ReqDDSLocalFromRmt_LSB 0x1A
#define QIB_7322_IBCStatusB_1_ReqDDSLocalFromRmt_MSB 0x1D
#define QIB_7322_IBCStatusB_1_ReqDDSLocalFromRmt_RMASK 0xF
#define QIB_7322_IBCStatusB_1_LinkRoundTripLatency_LSB 0x0
#define QIB_7322_IBCStatusB_1_LinkRoundTripLatency_MSB 0x19
#define QIB_7322_IBCStatusB_1_LinkRoundTripLatency_RMASK 0x3FFFFFF

#define QIB_7322_IBCCtrlA_1_OFFS 0x2560
#define QIB_7322_IBCCtrlA_1_DEF 0x0000000000000000
#define QIB_7322_IBCCtrlA_1_Loopback_LSB 0x3F
#define QIB_7322_IBCCtrlA_1_Loopback_MSB 0x3F
#define QIB_7322_IBCCtrlA_1_Loopback_RMASK 0x1
#define QIB_7322_IBCCtrlA_1_LinkDownDefaultState_LSB 0x3E
#define QIB_7322_IBCCtrlA_1_LinkDownDefaultState_MSB 0x3E
#define QIB_7322_IBCCtrlA_1_LinkDownDefaultState_RMASK 0x1
#define QIB_7322_IBCCtrlA_1_IBLinkEn_LSB 0x3D
#define QIB_7322_IBCCtrlA_1_IBLinkEn_MSB 0x3D
#define QIB_7322_IBCCtrlA_1_IBLinkEn_RMASK 0x1
#define QIB_7322_IBCCtrlA_1_IBStatIntReductionEn_LSB 0x3C
#define QIB_7322_IBCCtrlA_1_IBStatIntReductionEn_MSB 0x3C
#define QIB_7322_IBCCtrlA_1_IBStatIntReductionEn_RMASK 0x1
#define QIB_7322_IBCCtrlA_1_NumVLane_LSB 0x30
#define QIB_7322_IBCCtrlA_1_NumVLane_MSB 0x32
#define QIB_7322_IBCCtrlA_1_NumVLane_RMASK 0x7
#define QIB_7322_IBCCtrlA_1_OverrunThreshold_LSB 0x24
#define QIB_7322_IBCCtrlA_1_OverrunThreshold_MSB 0x27
#define QIB_7322_IBCCtrlA_1_OverrunThreshold_RMASK 0xF
#define QIB_7322_IBCCtrlA_1_PhyerrThreshold_LSB 0x20
#define QIB_7322_IBCCtrlA_1_PhyerrThreshold_MSB 0x23
#define QIB_7322_IBCCtrlA_1_PhyerrThreshold_RMASK 0xF
#define QIB_7322_IBCCtrlA_1_MaxPktLen_LSB 0x15
#define QIB_7322_IBCCtrlA_1_MaxPktLen_MSB 0x1F
#define QIB_7322_IBCCtrlA_1_MaxPktLen_RMASK 0x7FF
#define QIB_7322_IBCCtrlA_1_LinkCmd_LSB 0x13
#define QIB_7322_IBCCtrlA_1_LinkCmd_MSB 0x14
#define QIB_7322_IBCCtrlA_1_LinkCmd_RMASK 0x3
#define QIB_7322_IBCCtrlA_1_LinkInitCmd_LSB 0x10
#define QIB_7322_IBCCtrlA_1_LinkInitCmd_MSB 0x12
#define QIB_7322_IBCCtrlA_1_LinkInitCmd_RMASK 0x7
#define QIB_7322_IBCCtrlA_1_FlowCtrlWaterMark_LSB 0x8
#define QIB_7322_IBCCtrlA_1_FlowCtrlWaterMark_MSB 0xF
#define QIB_7322_IBCCtrlA_1_FlowCtrlWaterMark_RMASK 0xFF
#define QIB_7322_IBCCtrlA_1_FlowCtrlPeriod_LSB 0x0
#define QIB_7322_IBCCtrlA_1_FlowCtrlPeriod_MSB 0x7
#define QIB_7322_IBCCtrlA_1_FlowCtrlPeriod_RMASK 0xFF

#define QIB_7322_IBCCtrlB_1_OFFS 0x2568
#define QIB_7322_IBCCtrlB_1_DEF 0x00000000000305FF
#define QIB_7322_IBCCtrlB_1_IB_DLID_MASK_LSB 0x30
#define QIB_7322_IBCCtrlB_1_IB_DLID_MASK_MSB 0x3F
#define QIB_7322_IBCCtrlB_1_IB_DLID_MASK_RMASK 0xFFFF
#define QIB_7322_IBCCtrlB_1_IB_DLID_LSB 0x20
#define QIB_7322_IBCCtrlB_1_IB_DLID_MSB 0x2F
#define QIB_7322_IBCCtrlB_1_IB_DLID_RMASK 0xFFFF
#define QIB_7322_IBCCtrlB_1_IB_ENABLE_FILT_DPKT_LSB 0x1B
#define QIB_7322_IBCCtrlB_1_IB_ENABLE_FILT_DPKT_MSB 0x1B
#define QIB_7322_IBCCtrlB_1_IB_ENABLE_FILT_DPKT_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_HRTBT_REQ_LSB 0x1A
#define QIB_7322_IBCCtrlB_1_HRTBT_REQ_MSB 0x1A
#define QIB_7322_IBCCtrlB_1_HRTBT_REQ_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_HRTBT_PORT_LSB 0x12
#define QIB_7322_IBCCtrlB_1_HRTBT_PORT_MSB 0x19
#define QIB_7322_IBCCtrlB_1_HRTBT_PORT_RMASK 0xFF
#define QIB_7322_IBCCtrlB_1_HRTBT_AUTO_LSB 0x11
#define QIB_7322_IBCCtrlB_1_HRTBT_AUTO_MSB 0x11
#define QIB_7322_IBCCtrlB_1_HRTBT_AUTO_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_HRTBT_ENB_LSB 0x10
#define QIB_7322_IBCCtrlB_1_HRTBT_ENB_MSB 0x10
#define QIB_7322_IBCCtrlB_1_HRTBT_ENB_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_SD_DDS_LSB 0xC
#define QIB_7322_IBCCtrlB_1_SD_DDS_MSB 0xF
#define QIB_7322_IBCCtrlB_1_SD_DDS_RMASK 0xF
#define QIB_7322_IBCCtrlB_1_SD_DDSV_LSB 0xB
#define QIB_7322_IBCCtrlB_1_SD_DDSV_MSB 0xB
#define QIB_7322_IBCCtrlB_1_SD_DDSV_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_SD_ADD_ENB_LSB 0xA
#define QIB_7322_IBCCtrlB_1_SD_ADD_ENB_MSB 0xA
#define QIB_7322_IBCCtrlB_1_SD_ADD_ENB_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_SD_RX_EQUAL_ENABLE_LSB 0x9
#define QIB_7322_IBCCtrlB_1_SD_RX_EQUAL_ENABLE_MSB 0x9
#define QIB_7322_IBCCtrlB_1_SD_RX_EQUAL_ENABLE_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_IB_LANE_REV_SUPPORTED_LSB 0x8
#define QIB_7322_IBCCtrlB_1_IB_LANE_REV_SUPPORTED_MSB 0x8
#define QIB_7322_IBCCtrlB_1_IB_LANE_REV_SUPPORTED_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_IB_POLARITY_REV_SUPP_LSB 0x7
#define QIB_7322_IBCCtrlB_1_IB_POLARITY_REV_SUPP_MSB 0x7
#define QIB_7322_IBCCtrlB_1_IB_POLARITY_REV_SUPP_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_IB_NUM_CHANNELS_LSB 0x5
#define QIB_7322_IBCCtrlB_1_IB_NUM_CHANNELS_MSB 0x6
#define QIB_7322_IBCCtrlB_1_IB_NUM_CHANNELS_RMASK 0x3
#define QIB_7322_IBCCtrlB_1_SD_SPEED_QDR_LSB 0x4
#define QIB_7322_IBCCtrlB_1_SD_SPEED_QDR_MSB 0x4
#define QIB_7322_IBCCtrlB_1_SD_SPEED_QDR_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_SD_SPEED_DDR_LSB 0x3
#define QIB_7322_IBCCtrlB_1_SD_SPEED_DDR_MSB 0x3
#define QIB_7322_IBCCtrlB_1_SD_SPEED_DDR_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_SD_SPEED_SDR_LSB 0x2
#define QIB_7322_IBCCtrlB_1_SD_SPEED_SDR_MSB 0x2
#define QIB_7322_IBCCtrlB_1_SD_SPEED_SDR_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_SD_SPEED_LSB 0x1
#define QIB_7322_IBCCtrlB_1_SD_SPEED_MSB 0x1
#define QIB_7322_IBCCtrlB_1_SD_SPEED_RMASK 0x1
#define QIB_7322_IBCCtrlB_1_IB_ENHANCED_MODE_LSB 0x0
#define QIB_7322_IBCCtrlB_1_IB_ENHANCED_MODE_MSB 0x0
#define QIB_7322_IBCCtrlB_1_IB_ENHANCED_MODE_RMASK 0x1

#define QIB_7322_IBCCtrlC_1_OFFS 0x2570
#define QIB_7322_IBCCtrlC_1_DEF 0x0000000000000301
#define QIB_7322_IBCCtrlC_1_IB_BACK_PORCH_LSB 0x5
#define QIB_7322_IBCCtrlC_1_IB_BACK_PORCH_MSB 0x9
#define QIB_7322_IBCCtrlC_1_IB_BACK_PORCH_RMASK 0x1F
#define QIB_7322_IBCCtrlC_1_IB_FRONT_PORCH_LSB 0x0
#define QIB_7322_IBCCtrlC_1_IB_FRONT_PORCH_MSB 0x4
#define QIB_7322_IBCCtrlC_1_IB_FRONT_PORCH_RMASK 0x1F

#define QIB_7322_HRTBT_GUID_1_OFFS 0x2588
#define QIB_7322_HRTBT_GUID_1_DEF 0x0000000000000000

#define QIB_7322_IB_SDTEST_IF_TX_1_OFFS 0x2590
#define QIB_7322_IB_SDTEST_IF_TX_1_DEF 0x0000000000000000
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_RX_CFG_LSB 0x30
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_RX_CFG_MSB 0x3F
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_RX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_TX_CFG_LSB 0x20
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_TX_CFG_MSB 0x2F
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_TX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_SPEED_LSB 0xD
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_SPEED_MSB 0xF
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_SPEED_RMASK 0x7
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_OPCODE_LSB 0xB
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_OPCODE_MSB 0xC
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_TX_OPCODE_RMASK 0x3
#define QIB_7322_IB_SDTEST_IF_TX_1_CREDIT_CHANGE_LSB 0x4
#define QIB_7322_IB_SDTEST_IF_TX_1_CREDIT_CHANGE_MSB 0x4
#define QIB_7322_IB_SDTEST_IF_TX_1_CREDIT_CHANGE_RMASK 0x1
#define QIB_7322_IB_SDTEST_IF_TX_1_VL_CAP_LSB 0x2
#define QIB_7322_IB_SDTEST_IF_TX_1_VL_CAP_MSB 0x3
#define QIB_7322_IB_SDTEST_IF_TX_1_VL_CAP_RMASK 0x3
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_3_TX_VALID_LSB 0x1
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_3_TX_VALID_MSB 0x1
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_3_TX_VALID_RMASK 0x1
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_T_TX_VALID_LSB 0x0
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_T_TX_VALID_MSB 0x0
#define QIB_7322_IB_SDTEST_IF_TX_1_TS_T_TX_VALID_RMASK 0x1

#define QIB_7322_IB_SDTEST_IF_RX_1_OFFS 0x2598
#define QIB_7322_IB_SDTEST_IF_RX_1_DEF 0x0000000000000000
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_RX_CFG_LSB 0x30
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_RX_CFG_MSB 0x3F
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_RX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_TX_CFG_LSB 0x20
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_TX_CFG_MSB 0x2F
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_TX_CFG_RMASK 0xFFFF
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_B_LSB 0x18
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_B_MSB 0x1F
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_B_RMASK 0xFF
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_A_LSB 0x10
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_A_MSB 0x17
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_RX_A_RMASK 0xFF
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_3_RX_VALID_LSB 0x1
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_3_RX_VALID_MSB 0x1
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_3_RX_VALID_RMASK 0x1
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_T_RX_VALID_LSB 0x0
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_T_RX_VALID_MSB 0x0
#define QIB_7322_IB_SDTEST_IF_RX_1_TS_T_RX_VALID_RMASK 0x1

#define QIB_7322_IBNCModeCtrl_1_OFFS 0x25B8
#define QIB_7322_IBNCModeCtrl_1_DEF 0x0000000000000000
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapRemoteForce_LSB 0x22
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapRemoteForce_MSB 0x22
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapRemoteForce_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapRemoteMask_LSB 0x21
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapRemoteMask_MSB 0x21
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapRemoteMask_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapLocal_LSB 0x20
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapLocal_MSB 0x20
#define QIB_7322_IBNCModeCtrl_1_ScrambleCapLocal_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_1_TSMCode_TS2_LSB 0x11
#define QIB_7322_IBNCModeCtrl_1_TSMCode_TS2_MSB 0x19
#define QIB_7322_IBNCModeCtrl_1_TSMCode_TS2_RMASK 0x1FF
#define QIB_7322_IBNCModeCtrl_1_TSMCode_TS1_LSB 0x8
#define QIB_7322_IBNCModeCtrl_1_TSMCode_TS1_MSB 0x10
#define QIB_7322_IBNCModeCtrl_1_TSMCode_TS1_RMASK 0x1FF
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_ignore_TSM_on_rx_LSB 0x2
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_ignore_TSM_on_rx_MSB 0x2
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_ignore_TSM_on_rx_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_send_TS2_LSB 0x1
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_send_TS2_MSB 0x1
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_send_TS2_RMASK 0x1
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_send_TS1_LSB 0x0
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_send_TS1_MSB 0x0
#define QIB_7322_IBNCModeCtrl_1_TSMEnable_send_TS1_RMASK 0x1

#define QIB_7322_IBSerdesStatus_1_OFFS 0x25D0
#define QIB_7322_IBSerdesStatus_1_DEF 0x0000000000000000

#define QIB_7322_IBPCSConfig_1_OFFS 0x25D8
#define QIB_7322_IBPCSConfig_1_DEF 0x0000000000000007
#define QIB_7322_IBPCSConfig_1_link_sync_mask_LSB 0x9
#define QIB_7322_IBPCSConfig_1_link_sync_mask_MSB 0x12
#define QIB_7322_IBPCSConfig_1_link_sync_mask_RMASK 0x3FF
#define QIB_7322_IBPCSConfig_1_xcv_rreset_LSB 0x2
#define QIB_7322_IBPCSConfig_1_xcv_rreset_MSB 0x2
#define QIB_7322_IBPCSConfig_1_xcv_rreset_RMASK 0x1
#define QIB_7322_IBPCSConfig_1_xcv_treset_LSB 0x1
#define QIB_7322_IBPCSConfig_1_xcv_treset_MSB 0x1
#define QIB_7322_IBPCSConfig_1_xcv_treset_RMASK 0x1
#define QIB_7322_IBPCSConfig_1_tx_rx_reset_LSB 0x0
#define QIB_7322_IBPCSConfig_1_tx_rx_reset_MSB 0x0
#define QIB_7322_IBPCSConfig_1_tx_rx_reset_RMASK 0x1

#define QIB_7322_IBSerdesCtrl_1_OFFS 0x25E0
#define QIB_7322_IBSerdesCtrl_1_DEF 0x0000000000FFA00F
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_QDR_LSB 0x1A
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_QDR_MSB 0x1A
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_QDR_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_DDR_LSB 0x19
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_DDR_MSB 0x19
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_DDR_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_SDR_LSB 0x18
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_SDR_MSB 0x18
#define QIB_7322_IBSerdesCtrl_1_DISABLE_RXLATOFF_SDR_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_CHANNEL_RESET_N_LSB 0x14
#define QIB_7322_IBSerdesCtrl_1_CHANNEL_RESET_N_MSB 0x17
#define QIB_7322_IBSerdesCtrl_1_CHANNEL_RESET_N_RMASK 0xF
#define QIB_7322_IBSerdesCtrl_1_CGMODE_LSB 0x10
#define QIB_7322_IBSerdesCtrl_1_CGMODE_MSB 0x13
#define QIB_7322_IBSerdesCtrl_1_CGMODE_RMASK 0xF
#define QIB_7322_IBSerdesCtrl_1_IB_LAT_MODE_LSB 0xF
#define QIB_7322_IBSerdesCtrl_1_IB_LAT_MODE_MSB 0xF
#define QIB_7322_IBSerdesCtrl_1_IB_LAT_MODE_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_RXLOSEN_LSB 0xD
#define QIB_7322_IBSerdesCtrl_1_RXLOSEN_MSB 0xD
#define QIB_7322_IBSerdesCtrl_1_RXLOSEN_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_LPEN_LSB 0xC
#define QIB_7322_IBSerdesCtrl_1_LPEN_MSB 0xC
#define QIB_7322_IBSerdesCtrl_1_LPEN_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_PLLPD_LSB 0xB
#define QIB_7322_IBSerdesCtrl_1_PLLPD_MSB 0xB
#define QIB_7322_IBSerdesCtrl_1_PLLPD_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_TXPD_LSB 0xA
#define QIB_7322_IBSerdesCtrl_1_TXPD_MSB 0xA
#define QIB_7322_IBSerdesCtrl_1_TXPD_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_RXPD_LSB 0x9
#define QIB_7322_IBSerdesCtrl_1_RXPD_MSB 0x9
#define QIB_7322_IBSerdesCtrl_1_RXPD_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_TXIDLE_LSB 0x8
#define QIB_7322_IBSerdesCtrl_1_TXIDLE_MSB 0x8
#define QIB_7322_IBSerdesCtrl_1_TXIDLE_RMASK 0x1
#define QIB_7322_IBSerdesCtrl_1_CMODE_LSB 0x0
#define QIB_7322_IBSerdesCtrl_1_CMODE_MSB 0x6
#define QIB_7322_IBSerdesCtrl_1_CMODE_RMASK 0x7F

#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_OFFS 0x2600
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_DEF 0x0000000000000000
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_tx_override_deemphasis_select_LSB 0x1F
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_tx_override_deemphasis_select_MSB 0x1F
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_tx_override_deemphasis_select_RMASK 0x1
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_reset_tx_deemphasis_override_LSB 0x1E
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_reset_tx_deemphasis_override_MSB 0x1E
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_reset_tx_deemphasis_override_RMASK 0x1
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txampcntl_d2a_LSB 0xE
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txampcntl_d2a_MSB 0x11
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txampcntl_d2a_RMASK 0xF
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txc0_ena_LSB 0x9
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txc0_ena_MSB 0xD
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txc0_ena_RMASK 0x1F
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcp1_ena_LSB 0x5
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcp1_ena_MSB 0x8
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcp1_ena_RMASK 0xF
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcn1_xtra_emph0_LSB 0x3
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcn1_xtra_emph0_MSB 0x4
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcn1_xtra_emph0_RMASK 0x3
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcn1_ena_LSB 0x0
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcn1_ena_MSB 0x2
#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_txcn1_ena_RMASK 0x7

#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_OFFS 0x2640
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenagain_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenale_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_static_disable_rxenadfe_sdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_OFFS 0x2648
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenagain_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenale_sdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_dyn_disable_rxenadfe_sdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_OFFS 0x2650
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenagain_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenale_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_static_disable_rxenadfe_ddr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_OFFS 0x2658
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenagain_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenale_ddr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_dyn_disable_rxenadfe_ddr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_OFFS 0x2660
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenagain_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenale_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_static_disable_rxenadfe_qdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_OFFS 0x2668
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_DEF 0x0000000000000000
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch3_LSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch3_MSB 0x27
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch2_LSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch2_MSB 0x26
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch1_LSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch1_MSB 0x25
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch0_LSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch0_MSB 0x24
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenagain_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch3_LSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch3_MSB 0x23
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch3_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch2_LSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch2_MSB 0x22
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch2_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch1_LSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch1_MSB 0x21
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch1_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch0_LSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch0_MSB 0x20
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenale_qdr_ch0_RMASK 0x1
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch3_LSB 0x18
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch3_MSB 0x1F
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch3_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch2_LSB 0x10
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch2_MSB 0x17
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch2_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch1_LSB 0x8
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch1_MSB 0xF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch1_RMASK 0xFF
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch0_LSB 0x0
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch0_MSB 0x7
#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_dyn_disable_rxenadfe_qdr_ch0_RMASK 0xFF

#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_1_OFFS 0x2670
#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_1_DEF 0x0000000000000000

#define QIB_7322_RxBufrUnCorErrLogA_1_OFFS 0x2800
#define QIB_7322_RxBufrUnCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogA_1_RxBufrUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogA_1_RxBufrUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogA_1_RxBufrUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogB_1_OFFS 0x2808
#define QIB_7322_RxBufrUnCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogB_1_RxBufrUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogB_1_RxBufrUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogB_1_RxBufrUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogC_1_OFFS 0x2810
#define QIB_7322_RxBufrUnCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogC_1_RxBufrUnCorErrData_191_128_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogC_1_RxBufrUnCorErrData_191_128_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogC_1_RxBufrUnCorErrData_191_128_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogD_1_OFFS 0x2818
#define QIB_7322_RxBufrUnCorErrLogD_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogD_1_RxBufrUnCorErrData_255_192_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogD_1_RxBufrUnCorErrData_255_192_MSB 0x3F
#define QIB_7322_RxBufrUnCorErrLogD_1_RxBufrUnCorErrData_255_192_RMASK 0x0

#define QIB_7322_RxBufrUnCorErrLogE_1_OFFS 0x2820
#define QIB_7322_RxBufrUnCorErrLogE_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrAddr_15_0_LSB 0x28
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrAddr_15_0_MSB 0x37
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrAddr_15_0_RMASK 0xFFFF
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrCheckBit_36_0_LSB 0x3
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrCheckBit_36_0_MSB 0x27
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrCheckBit_36_0_RMASK 0x1FFFFFFFFF
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrData_258_256_LSB 0x0
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrData_258_256_MSB 0x2
#define QIB_7322_RxBufrUnCorErrLogE_1_RxBufrUnCorErrData_258_256_RMASK 0x7

#define QIB_7322_RxFlagUnCorErrLogA_1_OFFS 0x2828
#define QIB_7322_RxFlagUnCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxFlagUnCorErrLogA_1_RxFlagUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxFlagUnCorErrLogA_1_RxFlagUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxFlagUnCorErrLogA_1_RxFlagUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxFlagUnCorErrLogB_1_OFFS 0x2830
#define QIB_7322_RxFlagUnCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxFlagUnCorErrLogB_1_RxFlagUnCorErrAddr_12_0_LSB 0x8
#define QIB_7322_RxFlagUnCorErrLogB_1_RxFlagUnCorErrAddr_12_0_MSB 0x14
#define QIB_7322_RxFlagUnCorErrLogB_1_RxFlagUnCorErrAddr_12_0_RMASK 0x1FFF
#define QIB_7322_RxFlagUnCorErrLogB_1_RxFlagUnCorErrCheckBit_7_0_LSB 0x0
#define QIB_7322_RxFlagUnCorErrLogB_1_RxFlagUnCorErrCheckBit_7_0_MSB 0x7
#define QIB_7322_RxFlagUnCorErrLogB_1_RxFlagUnCorErrCheckBit_7_0_RMASK 0xFF

#define QIB_7322_RxLkupiqUnCorErrLogA_1_OFFS 0x2840
#define QIB_7322_RxLkupiqUnCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqUnCorErrLogA_1_RxLkupiqUnCorErrCheckBit_7_0_LSB 0x2E
#define QIB_7322_RxLkupiqUnCorErrLogA_1_RxLkupiqUnCorErrCheckBit_7_0_MSB 0x35
#define QIB_7322_RxLkupiqUnCorErrLogA_1_RxLkupiqUnCorErrCheckBit_7_0_RMASK 0xFF
#define QIB_7322_RxLkupiqUnCorErrLogA_1_RxLkupiqUnCorErrData_45_0_LSB 0x0
#define QIB_7322_RxLkupiqUnCorErrLogA_1_RxLkupiqUnCorErrData_45_0_MSB 0x2D
#define QIB_7322_RxLkupiqUnCorErrLogA_1_RxLkupiqUnCorErrData_45_0_RMASK 0x3FFFFFFFFFFF

#define QIB_7322_RxLkupiqUnCorErrLogB_1_OFFS 0x2848
#define QIB_7322_RxLkupiqUnCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqUnCorErrLogB_1_RxLkupiqUnCorErrAddr_12_0_LSB 0x0
#define QIB_7322_RxLkupiqUnCorErrLogB_1_RxLkupiqUnCorErrAddr_12_0_MSB 0xC
#define QIB_7322_RxLkupiqUnCorErrLogB_1_RxLkupiqUnCorErrAddr_12_0_RMASK 0x1FFF

#define QIB_7322_RxHdrFifoUnCorErrLogA_1_OFFS 0x2850
#define QIB_7322_RxHdrFifoUnCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoUnCorErrLogA_1_RxHdrFifoUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxHdrFifoUnCorErrLogA_1_RxHdrFifoUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxHdrFifoUnCorErrLogA_1_RxHdrFifoUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxHdrFifoUnCorErrLogB_1_OFFS 0x2858
#define QIB_7322_RxHdrFifoUnCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoUnCorErrLogB_1_RxHdrFifoUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RxHdrFifoUnCorErrLogB_1_RxHdrFifoUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxHdrFifoUnCorErrLogB_1_RxHdrFifoUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxHdrFifoUnCorErrLogC_1_OFFS 0x2860
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_RxHdrFifoUnCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_RxHdrFifoUnCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_RxHdrFifoUnCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_RxHdrFifoUnCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_RxHdrFifoUnCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxHdrFifoUnCorErrLogC_1_RxHdrFifoUnCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_RxDataFifoUnCorErrLogA_1_OFFS 0x2868
#define QIB_7322_RxDataFifoUnCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoUnCorErrLogA_1_RxDataFifoUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RxDataFifoUnCorErrLogA_1_RxDataFifoUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxDataFifoUnCorErrLogA_1_RxDataFifoUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxDataFifoUnCorErrLogB_1_OFFS 0x2870
#define QIB_7322_RxDataFifoUnCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoUnCorErrLogB_1_RxDataFifoUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RxDataFifoUnCorErrLogB_1_RxDataFifoUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxDataFifoUnCorErrLogB_1_RxDataFifoUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxDataFifoUnCorErrLogC_1_OFFS 0x2878
#define QIB_7322_RxDataFifoUnCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoUnCorErrLogC_1_RxDataFifoUnCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxDataFifoUnCorErrLogC_1_RxDataFifoUnCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxDataFifoUnCorErrLogC_1_RxDataFifoUnCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxDataFifoUnCorErrLogC_1_RxDataFifoUnCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxDataFifoUnCorErrLogC_1_RxDataFifoUnCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxDataFifoUnCorErrLogC_1_RxDataFifoUnCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_LaFifoArray0UnCorErrLog_1_OFFS 0x2880
#define QIB_7322_LaFifoArray0UnCorErrLog_1_DEF 0x0000000000000000
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrAddr_10_0_LSB 0x2E
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrAddr_10_0_MSB 0x38
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrCheckBit_10_0_LSB 0x23
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrCheckBit_10_0_MSB 0x2D
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrCheckBit_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrData_34_0_LSB 0x0
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrData_34_0_MSB 0x22
#define QIB_7322_LaFifoArray0UnCorErrLog_1_LaFifoArray0UnCorErrData_34_0_RMASK 0x7FFFFFFFF

#define QIB_7322_RmFifoArrayUnCorErrLogA_1_OFFS 0x28C0
#define QIB_7322_RmFifoArrayUnCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayUnCorErrLogA_1_RmFifoArrayUnCorErrData_63_0_LSB 0x0
#define QIB_7322_RmFifoArrayUnCorErrLogA_1_RmFifoArrayUnCorErrData_63_0_MSB 0x3F
#define QIB_7322_RmFifoArrayUnCorErrLogA_1_RmFifoArrayUnCorErrData_63_0_RMASK 0x0

#define QIB_7322_RmFifoArrayUnCorErrLogB_1_OFFS 0x28C8
#define QIB_7322_RmFifoArrayUnCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayUnCorErrLogB_1_RmFifoArrayUnCorErrData_127_64_LSB 0x0
#define QIB_7322_RmFifoArrayUnCorErrLogB_1_RmFifoArrayUnCorErrData_127_64_MSB 0x3F
#define QIB_7322_RmFifoArrayUnCorErrLogB_1_RmFifoArrayUnCorErrData_127_64_RMASK 0x0

#define QIB_7322_RmFifoArrayUnCorErrLogC_1_OFFS 0x28D0
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrDword_3_0_LSB 0x3C
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrDword_3_0_MSB 0x3F
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrDword_3_0_RMASK 0xF
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrAddr_13_0_LSB 0x1C
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrAddr_13_0_MSB 0x29
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_RmFifoArrayUnCorErrLogC_1_RmFifoArrayUnCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_RxBufrCorErrLogA_1_OFFS 0x2900
#define QIB_7322_RxBufrCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogA_1_RxBufrCorErrData_63_0_LSB 0x0
#define QIB_7322_RxBufrCorErrLogA_1_RxBufrCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogA_1_RxBufrCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogB_1_OFFS 0x2908
#define QIB_7322_RxBufrCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogB_1_RxBufrCorErrData_127_64_LSB 0x0
#define QIB_7322_RxBufrCorErrLogB_1_RxBufrCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogB_1_RxBufrCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogC_1_OFFS 0x2910
#define QIB_7322_RxBufrCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogC_1_RxBufrCorErrData_191_128_LSB 0x0
#define QIB_7322_RxBufrCorErrLogC_1_RxBufrCorErrData_191_128_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogC_1_RxBufrCorErrData_191_128_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogD_1_OFFS 0x2918
#define QIB_7322_RxBufrCorErrLogD_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogD_1_RxBufrCorErrData_255_192_LSB 0x0
#define QIB_7322_RxBufrCorErrLogD_1_RxBufrCorErrData_255_192_MSB 0x3F
#define QIB_7322_RxBufrCorErrLogD_1_RxBufrCorErrData_255_192_RMASK 0x0

#define QIB_7322_RxBufrCorErrLogE_1_OFFS 0x2920
#define QIB_7322_RxBufrCorErrLogE_1_DEF 0x0000000000000000
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrAddr_15_0_LSB 0x28
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrAddr_15_0_MSB 0x37
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrAddr_15_0_RMASK 0xFFFF
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrCheckBit_36_0_LSB 0x3
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrCheckBit_36_0_MSB 0x27
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrCheckBit_36_0_RMASK 0x1FFFFFFFFF
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrData_258_256_LSB 0x0
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrData_258_256_MSB 0x2
#define QIB_7322_RxBufrCorErrLogE_1_RxBufrCorErrData_258_256_RMASK 0x7

#define QIB_7322_RxFlagCorErrLogA_1_OFFS 0x2928
#define QIB_7322_RxFlagCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxFlagCorErrLogA_1_RxFlagCorErrData_63_0_LSB 0x0
#define QIB_7322_RxFlagCorErrLogA_1_RxFlagCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxFlagCorErrLogA_1_RxFlagCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxFlagCorErrLogB_1_OFFS 0x2930
#define QIB_7322_RxFlagCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxFlagCorErrLogB_1_RxFlagCorErrAddr_12_0_LSB 0x8
#define QIB_7322_RxFlagCorErrLogB_1_RxFlagCorErrAddr_12_0_MSB 0x14
#define QIB_7322_RxFlagCorErrLogB_1_RxFlagCorErrAddr_12_0_RMASK 0x1FFF
#define QIB_7322_RxFlagCorErrLogB_1_RxFlagCorErrCheckBit_7_0_LSB 0x0
#define QIB_7322_RxFlagCorErrLogB_1_RxFlagCorErrCheckBit_7_0_MSB 0x7
#define QIB_7322_RxFlagCorErrLogB_1_RxFlagCorErrCheckBit_7_0_RMASK 0xFF

#define QIB_7322_RxLkupiqCorErrLogA_1_OFFS 0x2940
#define QIB_7322_RxLkupiqCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqCorErrLogA_1_RxLkupiqCorErrCheckBit_7_0_LSB 0x2E
#define QIB_7322_RxLkupiqCorErrLogA_1_RxLkupiqCorErrCheckBit_7_0_MSB 0x35
#define QIB_7322_RxLkupiqCorErrLogA_1_RxLkupiqCorErrCheckBit_7_0_RMASK 0xFF
#define QIB_7322_RxLkupiqCorErrLogA_1_RxLkupiqCorErrData_45_0_LSB 0x0
#define QIB_7322_RxLkupiqCorErrLogA_1_RxLkupiqCorErrData_45_0_MSB 0x2D
#define QIB_7322_RxLkupiqCorErrLogA_1_RxLkupiqCorErrData_45_0_RMASK 0x3FFFFFFFFFFF

#define QIB_7322_RxLkupiqCorErrLogB_1_OFFS 0x2948
#define QIB_7322_RxLkupiqCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxLkupiqCorErrLogB_1_RxLkupiqCorErrAddr_12_0_LSB 0x0
#define QIB_7322_RxLkupiqCorErrLogB_1_RxLkupiqCorErrAddr_12_0_MSB 0xC
#define QIB_7322_RxLkupiqCorErrLogB_1_RxLkupiqCorErrAddr_12_0_RMASK 0x1FFF

#define QIB_7322_RxHdrFifoCorErrLogA_1_OFFS 0x2950
#define QIB_7322_RxHdrFifoCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoCorErrLogA_1_RxHdrFifoCorErrData_63_0_LSB 0x0
#define QIB_7322_RxHdrFifoCorErrLogA_1_RxHdrFifoCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxHdrFifoCorErrLogA_1_RxHdrFifoCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxHdrFifoCorErrLogB_1_OFFS 0x2958
#define QIB_7322_RxHdrFifoCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoCorErrLogB_1_RxHdrFifoCorErrData_127_64_LSB 0x0
#define QIB_7322_RxHdrFifoCorErrLogB_1_RxHdrFifoCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxHdrFifoCorErrLogB_1_RxHdrFifoCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxHdrFifoCorErrLogC_1_OFFS 0x2960
#define QIB_7322_RxHdrFifoCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RxHdrFifoCorErrLogC_1_RxHdrFifoCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxHdrFifoCorErrLogC_1_RxHdrFifoCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxHdrFifoCorErrLogC_1_RxHdrFifoCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxHdrFifoCorErrLogC_1_RxHdrFifoCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxHdrFifoCorErrLogC_1_RxHdrFifoCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxHdrFifoCorErrLogC_1_RxHdrFifoCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_RxDataFifoCorErrLogA_1_OFFS 0x2968
#define QIB_7322_RxDataFifoCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoCorErrLogA_1_RxDataFifoCorErrData_63_0_LSB 0x0
#define QIB_7322_RxDataFifoCorErrLogA_1_RxDataFifoCorErrData_63_0_MSB 0x3F
#define QIB_7322_RxDataFifoCorErrLogA_1_RxDataFifoCorErrData_63_0_RMASK 0x0

#define QIB_7322_RxDataFifoCorErrLogB_1_OFFS 0x2970
#define QIB_7322_RxDataFifoCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoCorErrLogB_1_RxDataFifoCorErrData_127_64_LSB 0x0
#define QIB_7322_RxDataFifoCorErrLogB_1_RxDataFifoCorErrData_127_64_MSB 0x3F
#define QIB_7322_RxDataFifoCorErrLogB_1_RxDataFifoCorErrData_127_64_RMASK 0x0

#define QIB_7322_RxDataFifoCorErrLogC_1_OFFS 0x2978
#define QIB_7322_RxDataFifoCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RxDataFifoCorErrLogC_1_RxDataFifoCorErrAddr_10_0_LSB 0x10
#define QIB_7322_RxDataFifoCorErrLogC_1_RxDataFifoCorErrAddr_10_0_MSB 0x1A
#define QIB_7322_RxDataFifoCorErrLogC_1_RxDataFifoCorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_RxDataFifoCorErrLogC_1_RxDataFifoCorErrCheckBit_15_0_LSB 0x0
#define QIB_7322_RxDataFifoCorErrLogC_1_RxDataFifoCorErrCheckBit_15_0_MSB 0xF
#define QIB_7322_RxDataFifoCorErrLogC_1_RxDataFifoCorErrCheckBit_15_0_RMASK 0xFFFF

#define QIB_7322_LaFifoArray0CorErrLog_1_OFFS 0x2980
#define QIB_7322_LaFifoArray0CorErrLog_1_DEF 0x0000000000000000
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrAddr_10_0_LSB 0x2E
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrAddr_10_0_MSB 0x38
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrAddr_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrCheckBit_10_0_LSB 0x23
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrCheckBit_10_0_MSB 0x2D
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrCheckBit_10_0_RMASK 0x7FF
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrData_34_0_LSB 0x0
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrData_34_0_MSB 0x22
#define QIB_7322_LaFifoArray0CorErrLog_1_LaFifoArray0CorErrData_34_0_RMASK 0x7FFFFFFFF

#define QIB_7322_RmFifoArrayCorErrLogA_1_OFFS 0x29C0
#define QIB_7322_RmFifoArrayCorErrLogA_1_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayCorErrLogA_1_RmFifoArrayCorErrData_63_0_LSB 0x0
#define QIB_7322_RmFifoArrayCorErrLogA_1_RmFifoArrayCorErrData_63_0_MSB 0x3F
#define QIB_7322_RmFifoArrayCorErrLogA_1_RmFifoArrayCorErrData_63_0_RMASK 0x0

#define QIB_7322_RmFifoArrayCorErrLogB_1_OFFS 0x29C8
#define QIB_7322_RmFifoArrayCorErrLogB_1_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayCorErrLogB_1_RmFifoArrayCorErrData_127_64_LSB 0x0
#define QIB_7322_RmFifoArrayCorErrLogB_1_RmFifoArrayCorErrData_127_64_MSB 0x3F
#define QIB_7322_RmFifoArrayCorErrLogB_1_RmFifoArrayCorErrData_127_64_RMASK 0x0

#define QIB_7322_RmFifoArrayCorErrLogC_1_OFFS 0x29D0
#define QIB_7322_RmFifoArrayCorErrLogC_1_DEF 0x0000000000000000
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrDword_3_0_LSB 0x3C
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrDword_3_0_MSB 0x3F
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrDword_3_0_RMASK 0xF
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrAddr_13_0_LSB 0x1C
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrAddr_13_0_MSB 0x29
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrAddr_13_0_RMASK 0x3FFF
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrCheckBit_27_0_LSB 0x0
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrCheckBit_27_0_MSB 0x1B
#define QIB_7322_RmFifoArrayCorErrLogC_1_RmFifoArrayCorErrCheckBit_27_0_RMASK 0xFFFFFFF

#define QIB_7322_HighPriorityLimit_1_OFFS 0x2BC0
#define QIB_7322_HighPriorityLimit_1_DEF 0x0000000000000000
#define QIB_7322_HighPriorityLimit_1_Limit_LSB 0x0
#define QIB_7322_HighPriorityLimit_1_Limit_MSB 0x7
#define QIB_7322_HighPriorityLimit_1_Limit_RMASK 0xFF

#define QIB_7322_LowPriority0_1_OFFS 0x2C00
#define QIB_7322_LowPriority0_1_DEF 0x0000000000000000
#define QIB_7322_LowPriority0_1_VirtualLane_LSB 0x10
#define QIB_7322_LowPriority0_1_VirtualLane_MSB 0x12
#define QIB_7322_LowPriority0_1_VirtualLane_RMASK 0x7
#define QIB_7322_LowPriority0_1_Weight_LSB 0x0
#define QIB_7322_LowPriority0_1_Weight_MSB 0x7
#define QIB_7322_LowPriority0_1_Weight_RMASK 0xFF

#define QIB_7322_HighPriority0_1_OFFS 0x2E00
#define QIB_7322_HighPriority0_1_DEF 0x0000000000000000
#define QIB_7322_HighPriority0_1_VirtualLane_LSB 0x10
#define QIB_7322_HighPriority0_1_VirtualLane_MSB 0x12
#define QIB_7322_HighPriority0_1_VirtualLane_RMASK 0x7
#define QIB_7322_HighPriority0_1_Weight_LSB 0x0
#define QIB_7322_HighPriority0_1_Weight_MSB 0x7
#define QIB_7322_HighPriority0_1_Weight_RMASK 0xFF

#define QIB_7322_SendBufAvail0_OFFS 0x3000
#define QIB_7322_SendBufAvail0_DEF 0x0000000000000000
#define QIB_7322_SendBufAvail0_SendBuf_31_0_LSB 0x0
#define QIB_7322_SendBufAvail0_SendBuf_31_0_MSB 0x3F
#define QIB_7322_SendBufAvail0_SendBuf_31_0_RMASK 0x0

#define QIB_7322_MsixTable_OFFS 0x8000
#define QIB_7322_MsixTable_DEF 0x0000000000000000

#define QIB_7322_MsixPba_OFFS 0x9000
#define QIB_7322_MsixPba_DEF 0x0000000000000000

#define QIB_7322_LAMemory_OFFS 0xA000
#define QIB_7322_LAMemory_DEF 0x0000000000000000

#define QIB_7322_LBIntCnt_OFFS 0x11000
#define QIB_7322_LBIntCnt_DEF 0x0000000000000000

#define QIB_7322_LBFlowStallCnt_OFFS 0x11008
#define QIB_7322_LBFlowStallCnt_DEF 0x0000000000000000

#define QIB_7322_RxTIDFullErrCnt_OFFS 0x110D0
#define QIB_7322_RxTIDFullErrCnt_DEF 0x0000000000000000

#define QIB_7322_RxTIDValidErrCnt_OFFS 0x110D8
#define QIB_7322_RxTIDValidErrCnt_DEF 0x0000000000000000

#define QIB_7322_RxP0HdrEgrOvflCnt_OFFS 0x110E8
#define QIB_7322_RxP0HdrEgrOvflCnt_DEF 0x0000000000000000

#define QIB_7322_PcieRetryBufDiagQwordCnt_OFFS 0x111A0
#define QIB_7322_PcieRetryBufDiagQwordCnt_DEF 0x0000000000000000

#define QIB_7322_RxTidFlowDropCnt_OFFS 0x111E0
#define QIB_7322_RxTidFlowDropCnt_DEF 0x0000000000000000

#define QIB_7322_LBIntCnt_0_OFFS 0x12000
#define QIB_7322_LBIntCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxCreditUpToDateTimeOut_0_OFFS 0x12008
#define QIB_7322_TxCreditUpToDateTimeOut_0_DEF 0x0000000000000000

#define QIB_7322_TxSDmaDescCnt_0_OFFS 0x12010
#define QIB_7322_TxSDmaDescCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxUnsupVLErrCnt_0_OFFS 0x12018
#define QIB_7322_TxUnsupVLErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxDataPktCnt_0_OFFS 0x12020
#define QIB_7322_TxDataPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxFlowPktCnt_0_OFFS 0x12028
#define QIB_7322_TxFlowPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxDwordCnt_0_OFFS 0x12030
#define QIB_7322_TxDwordCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxLenErrCnt_0_OFFS 0x12038
#define QIB_7322_TxLenErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxMaxMinLenErrCnt_0_OFFS 0x12040
#define QIB_7322_TxMaxMinLenErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxUnderrunCnt_0_OFFS 0x12048
#define QIB_7322_TxUnderrunCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxFlowStallCnt_0_OFFS 0x12050
#define QIB_7322_TxFlowStallCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxDroppedPktCnt_0_OFFS 0x12058
#define QIB_7322_TxDroppedPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxDroppedPktCnt_0_OFFS 0x12060
#define QIB_7322_RxDroppedPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxDataPktCnt_0_OFFS 0x12068
#define QIB_7322_RxDataPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxFlowPktCnt_0_OFFS 0x12070
#define QIB_7322_RxFlowPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxDwordCnt_0_OFFS 0x12078
#define QIB_7322_RxDwordCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxLenErrCnt_0_OFFS 0x12080
#define QIB_7322_RxLenErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxMaxMinLenErrCnt_0_OFFS 0x12088
#define QIB_7322_RxMaxMinLenErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxICRCErrCnt_0_OFFS 0x12090
#define QIB_7322_RxICRCErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxVCRCErrCnt_0_OFFS 0x12098
#define QIB_7322_RxVCRCErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxFlowCtrlViolCnt_0_OFFS 0x120A0
#define QIB_7322_RxFlowCtrlViolCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxVersionErrCnt_0_OFFS 0x120A8
#define QIB_7322_RxVersionErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxLinkMalformCnt_0_OFFS 0x120B0
#define QIB_7322_RxLinkMalformCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxEBPCnt_0_OFFS 0x120B8
#define QIB_7322_RxEBPCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxLPCRCErrCnt_0_OFFS 0x120C0
#define QIB_7322_RxLPCRCErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxBufOvflCnt_0_OFFS 0x120C8
#define QIB_7322_RxBufOvflCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxLenTruncateCnt_0_OFFS 0x120D0
#define QIB_7322_RxLenTruncateCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxPKeyMismatchCnt_0_OFFS 0x120E0
#define QIB_7322_RxPKeyMismatchCnt_0_DEF 0x0000000000000000

#define QIB_7322_IBLinkDownedCnt_0_OFFS 0x12180
#define QIB_7322_IBLinkDownedCnt_0_DEF 0x0000000000000000

#define QIB_7322_IBSymbolErrCnt_0_OFFS 0x12188
#define QIB_7322_IBSymbolErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_IBStatusChangeCnt_0_OFFS 0x12190
#define QIB_7322_IBStatusChangeCnt_0_DEF 0x0000000000000000

#define QIB_7322_IBLinkErrRecoveryCnt_0_OFFS 0x12198
#define QIB_7322_IBLinkErrRecoveryCnt_0_DEF 0x0000000000000000

#define QIB_7322_ExcessBufferOvflCnt_0_OFFS 0x121A8
#define QIB_7322_ExcessBufferOvflCnt_0_DEF 0x0000000000000000

#define QIB_7322_LocalLinkIntegrityErrCnt_0_OFFS 0x121B0
#define QIB_7322_LocalLinkIntegrityErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxVlErrCnt_0_OFFS 0x121B8
#define QIB_7322_RxVlErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxDlidFltrCnt_0_OFFS 0x121C0
#define QIB_7322_RxDlidFltrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxVL15DroppedPktCnt_0_OFFS 0x121C8
#define QIB_7322_RxVL15DroppedPktCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxOtherLocalPhyErrCnt_0_OFFS 0x121D0
#define QIB_7322_RxOtherLocalPhyErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_RxQPInvalidContextCnt_0_OFFS 0x121D8
#define QIB_7322_RxQPInvalidContextCnt_0_DEF 0x0000000000000000

#define QIB_7322_TxHeadersErrCnt_0_OFFS 0x121F8
#define QIB_7322_TxHeadersErrCnt_0_DEF 0x0000000000000000

#define QIB_7322_PSRcvDataCount_0_OFFS 0x12218
#define QIB_7322_PSRcvDataCount_0_DEF 0x0000000000000000

#define QIB_7322_PSRcvPktsCount_0_OFFS 0x12220
#define QIB_7322_PSRcvPktsCount_0_DEF 0x0000000000000000

#define QIB_7322_PSXmitDataCount_0_OFFS 0x12228
#define QIB_7322_PSXmitDataCount_0_DEF 0x0000000000000000

#define QIB_7322_PSXmitPktsCount_0_OFFS 0x12230
#define QIB_7322_PSXmitPktsCount_0_DEF 0x0000000000000000

#define QIB_7322_PSXmitWaitCount_0_OFFS 0x12238
#define QIB_7322_PSXmitWaitCount_0_DEF 0x0000000000000000

#define QIB_7322_LBIntCnt_1_OFFS 0x13000
#define QIB_7322_LBIntCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxCreditUpToDateTimeOut_1_OFFS 0x13008
#define QIB_7322_TxCreditUpToDateTimeOut_1_DEF 0x0000000000000000

#define QIB_7322_TxSDmaDescCnt_1_OFFS 0x13010
#define QIB_7322_TxSDmaDescCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxUnsupVLErrCnt_1_OFFS 0x13018
#define QIB_7322_TxUnsupVLErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxDataPktCnt_1_OFFS 0x13020
#define QIB_7322_TxDataPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxFlowPktCnt_1_OFFS 0x13028
#define QIB_7322_TxFlowPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxDwordCnt_1_OFFS 0x13030
#define QIB_7322_TxDwordCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxLenErrCnt_1_OFFS 0x13038
#define QIB_7322_TxLenErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxMaxMinLenErrCnt_1_OFFS 0x13040
#define QIB_7322_TxMaxMinLenErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxUnderrunCnt_1_OFFS 0x13048
#define QIB_7322_TxUnderrunCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxFlowStallCnt_1_OFFS 0x13050
#define QIB_7322_TxFlowStallCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxDroppedPktCnt_1_OFFS 0x13058
#define QIB_7322_TxDroppedPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxDroppedPktCnt_1_OFFS 0x13060
#define QIB_7322_RxDroppedPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxDataPktCnt_1_OFFS 0x13068
#define QIB_7322_RxDataPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxFlowPktCnt_1_OFFS 0x13070
#define QIB_7322_RxFlowPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxDwordCnt_1_OFFS 0x13078
#define QIB_7322_RxDwordCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxLenErrCnt_1_OFFS 0x13080
#define QIB_7322_RxLenErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxMaxMinLenErrCnt_1_OFFS 0x13088
#define QIB_7322_RxMaxMinLenErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxICRCErrCnt_1_OFFS 0x13090
#define QIB_7322_RxICRCErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxVCRCErrCnt_1_OFFS 0x13098
#define QIB_7322_RxVCRCErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxFlowCtrlViolCnt_1_OFFS 0x130A0
#define QIB_7322_RxFlowCtrlViolCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxVersionErrCnt_1_OFFS 0x130A8
#define QIB_7322_RxVersionErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxLinkMalformCnt_1_OFFS 0x130B0
#define QIB_7322_RxLinkMalformCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxEBPCnt_1_OFFS 0x130B8
#define QIB_7322_RxEBPCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxLPCRCErrCnt_1_OFFS 0x130C0
#define QIB_7322_RxLPCRCErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxBufOvflCnt_1_OFFS 0x130C8
#define QIB_7322_RxBufOvflCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxLenTruncateCnt_1_OFFS 0x130D0
#define QIB_7322_RxLenTruncateCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxPKeyMismatchCnt_1_OFFS 0x130E0
#define QIB_7322_RxPKeyMismatchCnt_1_DEF 0x0000000000000000

#define QIB_7322_IBLinkDownedCnt_1_OFFS 0x13180
#define QIB_7322_IBLinkDownedCnt_1_DEF 0x0000000000000000

#define QIB_7322_IBSymbolErrCnt_1_OFFS 0x13188
#define QIB_7322_IBSymbolErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_IBStatusChangeCnt_1_OFFS 0x13190
#define QIB_7322_IBStatusChangeCnt_1_DEF 0x0000000000000000

#define QIB_7322_IBLinkErrRecoveryCnt_1_OFFS 0x13198
#define QIB_7322_IBLinkErrRecoveryCnt_1_DEF 0x0000000000000000

#define QIB_7322_ExcessBufferOvflCnt_1_OFFS 0x131A8
#define QIB_7322_ExcessBufferOvflCnt_1_DEF 0x0000000000000000

#define QIB_7322_LocalLinkIntegrityErrCnt_1_OFFS 0x131B0
#define QIB_7322_LocalLinkIntegrityErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxVlErrCnt_1_OFFS 0x131B8
#define QIB_7322_RxVlErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxDlidFltrCnt_1_OFFS 0x131C0
#define QIB_7322_RxDlidFltrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxVL15DroppedPktCnt_1_OFFS 0x131C8
#define QIB_7322_RxVL15DroppedPktCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxOtherLocalPhyErrCnt_1_OFFS 0x131D0
#define QIB_7322_RxOtherLocalPhyErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_RxQPInvalidContextCnt_1_OFFS 0x131D8
#define QIB_7322_RxQPInvalidContextCnt_1_DEF 0x0000000000000000

#define QIB_7322_TxHeadersErrCnt_1_OFFS 0x131F8
#define QIB_7322_TxHeadersErrCnt_1_DEF 0x0000000000000000

#define QIB_7322_PSRcvDataCount_1_OFFS 0x13218
#define QIB_7322_PSRcvDataCount_1_DEF 0x0000000000000000

#define QIB_7322_PSRcvPktsCount_1_OFFS 0x13220
#define QIB_7322_PSRcvPktsCount_1_DEF 0x0000000000000000

#define QIB_7322_PSXmitDataCount_1_OFFS 0x13228
#define QIB_7322_PSXmitDataCount_1_DEF 0x0000000000000000

#define QIB_7322_PSXmitPktsCount_1_OFFS 0x13230
#define QIB_7322_PSXmitPktsCount_1_DEF 0x0000000000000000

#define QIB_7322_PSXmitWaitCount_1_OFFS 0x13238
#define QIB_7322_PSXmitWaitCount_1_DEF 0x0000000000000000

#define QIB_7322_RcvEgrArray_OFFS 0x14000
#define QIB_7322_RcvEgrArray_DEF 0x0000000000000000
#define QIB_7322_RcvEgrArray_RT_BufSize_LSB 0x25
#define QIB_7322_RcvEgrArray_RT_BufSize_MSB 0x27
#define QIB_7322_RcvEgrArray_RT_BufSize_RMASK 0x7
#define QIB_7322_RcvEgrArray_RT_Addr_LSB 0x0
#define QIB_7322_RcvEgrArray_RT_Addr_MSB 0x24
#define QIB_7322_RcvEgrArray_RT_Addr_RMASK 0x1FFFFFFFFF

#define QIB_7322_RcvTIDArray0_OFFS 0x50000
#define QIB_7322_RcvTIDArray0_DEF 0x0000000000000000
#define QIB_7322_RcvTIDArray0_RT_BufSize_LSB 0x25
#define QIB_7322_RcvTIDArray0_RT_BufSize_MSB 0x27
#define QIB_7322_RcvTIDArray0_RT_BufSize_RMASK 0x7
#define QIB_7322_RcvTIDArray0_RT_Addr_LSB 0x0
#define QIB_7322_RcvTIDArray0_RT_Addr_MSB 0x24
#define QIB_7322_RcvTIDArray0_RT_Addr_RMASK 0x1FFFFFFFFF

#define QIB_7322_SendPbcCache_OFFS 0x70000
#define QIB_7322_SendPbcCache_DEF 0x0000000000000000

#define QIB_7322_LaunchFIFO_v0p0_OFFS 0x72000
#define QIB_7322_LaunchFIFO_v0p0_DEF 0x0000000000000000

#define QIB_7322_LaunchElement_v15p0_OFFS 0x76000
#define QIB_7322_LaunchElement_v15p0_DEF 0x0000000000000000

#define QIB_7322_PreLaunchFIFO_0_OFFS 0x76100
#define QIB_7322_PreLaunchFIFO_0_DEF 0x0000000000000000

#define QIB_7322_ScoreBoard_0_OFFS 0x76200
#define QIB_7322_ScoreBoard_0_DEF 0x0000000000000000

#define QIB_7322_DescriptorFIFO_0_OFFS 0x76300
#define QIB_7322_DescriptorFIFO_0_DEF 0x0000000000000000

#define QIB_7322_LaunchFIFO_v0p1_OFFS 0x78000
#define QIB_7322_LaunchFIFO_v0p1_DEF 0x0000000000000000

#define QIB_7322_LaunchElement_v15p1_OFFS 0x7C000
#define QIB_7322_LaunchElement_v15p1_DEF 0x0000000000000000

#define QIB_7322_PreLaunchFIFO_1_OFFS 0x7C100
#define QIB_7322_PreLaunchFIFO_1_DEF 0x0000000000000000

#define QIB_7322_ScoreBoard_1_OFFS 0x7C200
#define QIB_7322_ScoreBoard_1_DEF 0x0000000000000000

#define QIB_7322_DescriptorFIFO_1_OFFS 0x7C300
#define QIB_7322_DescriptorFIFO_1_DEF 0x0000000000000000

#define QIB_7322_RcvBufA_0_OFFS 0x80000
#define QIB_7322_RcvBufA_0_DEF 0x0000000000000000

#define QIB_7322_RcvBufB_0_OFFS 0x88000
#define QIB_7322_RcvBufB_0_DEF 0x0000000000000000

#define QIB_7322_RcvFlags_0_OFFS 0x8A000
#define QIB_7322_RcvFlags_0_DEF 0x0000000000000000

#define QIB_7322_RcvLookupiqBuf_0_OFFS 0x8C000
#define QIB_7322_RcvLookupiqBuf_0_DEF 0x0000000000000000

#define QIB_7322_RcvDMADatBuf_0_OFFS 0x8E000
#define QIB_7322_RcvDMADatBuf_0_DEF 0x0000000000000000

#define QIB_7322_RcvDMAHdrBuf_0_OFFS 0x8E800
#define QIB_7322_RcvDMAHdrBuf_0_DEF 0x0000000000000000

#define QIB_7322_RcvBufA_1_OFFS 0x90000
#define QIB_7322_RcvBufA_1_DEF 0x0000000000000000

#define QIB_7322_RcvBufB_1_OFFS 0x98000
#define QIB_7322_RcvBufB_1_DEF 0x0000000000000000

#define QIB_7322_RcvFlags_1_OFFS 0x9A000
#define QIB_7322_RcvFlags_1_DEF 0x0000000000000000

#define QIB_7322_RcvLookupiqBuf_1_OFFS 0x9C000
#define QIB_7322_RcvLookupiqBuf_1_DEF 0x0000000000000000

#define QIB_7322_RcvDMADatBuf_1_OFFS 0x9E000
#define QIB_7322_RcvDMADatBuf_1_DEF 0x0000000000000000

#define QIB_7322_RcvDMAHdrBuf_1_OFFS 0x9E800
#define QIB_7322_RcvDMAHdrBuf_1_DEF 0x0000000000000000

#define QIB_7322_PCIERcvBuf_OFFS 0xA0000
#define QIB_7322_PCIERcvBuf_DEF 0x0000000000000000

#define QIB_7322_PCIERetryBuf_OFFS 0xA4000
#define QIB_7322_PCIERetryBuf_DEF 0x0000000000000000

#define QIB_7322_PCIERcvBufRdToWrAddr_OFFS 0xA8000
#define QIB_7322_PCIERcvBufRdToWrAddr_DEF 0x0000000000000000

#define QIB_7322_PCIERcvHdrRdToWrAddr_OFFS 0xB0000
#define QIB_7322_PCIERcvHdrRdToWrAddr_DEF 0x0000000000000000

#define QIB_7322_PCIECplBuf_OFFS 0xB8000
#define QIB_7322_PCIECplBuf_DEF 0x0000000000000000

#define QIB_7322_PCIECplHdr_OFFS 0xBC000
#define QIB_7322_PCIECplHdr_DEF 0x0000000000000000

#define QIB_7322_PCIERcvHdr_OFFS 0xBC200
#define QIB_7322_PCIERcvHdr_DEF 0x0000000000000000

#define QIB_7322_IBSD_DDS_MAP_TABLE_0_OFFS 0xD0000
#define QIB_7322_IBSD_DDS_MAP_TABLE_0_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_0_OFFS 0x100000
#define QIB_7322_SendBufMA_0_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_0_OFFS 0x100800
#define QIB_7322_SendBufEA_0_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_1_OFFS 0x101000
#define QIB_7322_SendBufMA_1_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_1_OFFS 0x101800
#define QIB_7322_SendBufEA_1_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_2_OFFS 0x102000
#define QIB_7322_SendBufMA_2_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_2_OFFS 0x102800
#define QIB_7322_SendBufEA_2_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_3_OFFS 0x103000
#define QIB_7322_SendBufMA_3_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_3_OFFS 0x103800
#define QIB_7322_SendBufEA_3_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_4_OFFS 0x104000
#define QIB_7322_SendBufMA_4_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_4_OFFS 0x104800
#define QIB_7322_SendBufEA_4_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_5_OFFS 0x105000
#define QIB_7322_SendBufMA_5_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_5_OFFS 0x105800
#define QIB_7322_SendBufEA_5_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_6_OFFS 0x106000
#define QIB_7322_SendBufMA_6_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_6_OFFS 0x106800
#define QIB_7322_SendBufEA_6_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_7_OFFS 0x107000
#define QIB_7322_SendBufMA_7_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_7_OFFS 0x107800
#define QIB_7322_SendBufEA_7_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_8_OFFS 0x108000
#define QIB_7322_SendBufMA_8_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_8_OFFS 0x108800
#define QIB_7322_SendBufEA_8_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_9_OFFS 0x109000
#define QIB_7322_SendBufMA_9_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_9_OFFS 0x109800
#define QIB_7322_SendBufEA_9_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_10_OFFS 0x10A000
#define QIB_7322_SendBufMA_10_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_10_OFFS 0x10A800
#define QIB_7322_SendBufEA_10_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_11_OFFS 0x10B000
#define QIB_7322_SendBufMA_11_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_11_OFFS 0x10B800
#define QIB_7322_SendBufEA_11_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_12_OFFS 0x10C000
#define QIB_7322_SendBufMA_12_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_12_OFFS 0x10C800
#define QIB_7322_SendBufEA_12_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_13_OFFS 0x10D000
#define QIB_7322_SendBufMA_13_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_13_OFFS 0x10D800
#define QIB_7322_SendBufEA_13_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_14_OFFS 0x10E000
#define QIB_7322_SendBufMA_14_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_14_OFFS 0x10E800
#define QIB_7322_SendBufEA_14_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_15_OFFS 0x10F000
#define QIB_7322_SendBufMA_15_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_15_OFFS 0x10F800
#define QIB_7322_SendBufEA_15_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_16_OFFS 0x110000
#define QIB_7322_SendBufMA_16_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_16_OFFS 0x110800
#define QIB_7322_SendBufEA_16_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_17_OFFS 0x111000
#define QIB_7322_SendBufMA_17_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_17_OFFS 0x111800
#define QIB_7322_SendBufEA_17_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_18_OFFS 0x112000
#define QIB_7322_SendBufMA_18_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_18_OFFS 0x112800
#define QIB_7322_SendBufEA_18_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_19_OFFS 0x113000
#define QIB_7322_SendBufMA_19_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_19_OFFS 0x113800
#define QIB_7322_SendBufEA_19_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_20_OFFS 0x114000
#define QIB_7322_SendBufMA_20_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_20_OFFS 0x114800
#define QIB_7322_SendBufEA_20_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_21_OFFS 0x115000
#define QIB_7322_SendBufMA_21_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_21_OFFS 0x115800
#define QIB_7322_SendBufEA_21_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_22_OFFS 0x116000
#define QIB_7322_SendBufMA_22_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_22_OFFS 0x116800
#define QIB_7322_SendBufEA_22_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_23_OFFS 0x117000
#define QIB_7322_SendBufMA_23_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_23_OFFS 0x117800
#define QIB_7322_SendBufEA_23_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_24_OFFS 0x118000
#define QIB_7322_SendBufMA_24_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_24_OFFS 0x118800
#define QIB_7322_SendBufEA_24_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_25_OFFS 0x119000
#define QIB_7322_SendBufMA_25_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_25_OFFS 0x119800
#define QIB_7322_SendBufEA_25_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_26_OFFS 0x11A000
#define QIB_7322_SendBufMA_26_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_26_OFFS 0x11A800
#define QIB_7322_SendBufEA_26_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_27_OFFS 0x11B000
#define QIB_7322_SendBufMA_27_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_27_OFFS 0x11B800
#define QIB_7322_SendBufEA_27_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_28_OFFS 0x11C000
#define QIB_7322_SendBufMA_28_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_28_OFFS 0x11C800
#define QIB_7322_SendBufEA_28_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_29_OFFS 0x11D000
#define QIB_7322_SendBufMA_29_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_29_OFFS 0x11D800
#define QIB_7322_SendBufEA_29_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_30_OFFS 0x11E000
#define QIB_7322_SendBufMA_30_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_30_OFFS 0x11E800
#define QIB_7322_SendBufEA_30_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_31_OFFS 0x11F000
#define QIB_7322_SendBufMA_31_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_31_OFFS 0x11F800
#define QIB_7322_SendBufEA_31_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_32_OFFS 0x120000
#define QIB_7322_SendBufMA_32_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_32_OFFS 0x120800
#define QIB_7322_SendBufEA_32_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_33_OFFS 0x121000
#define QIB_7322_SendBufMA_33_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_33_OFFS 0x121800
#define QIB_7322_SendBufEA_33_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_34_OFFS 0x122000
#define QIB_7322_SendBufMA_34_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_34_OFFS 0x122800
#define QIB_7322_SendBufEA_34_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_35_OFFS 0x123000
#define QIB_7322_SendBufMA_35_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_35_OFFS 0x123800
#define QIB_7322_SendBufEA_35_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_36_OFFS 0x124000
#define QIB_7322_SendBufMA_36_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_36_OFFS 0x124800
#define QIB_7322_SendBufEA_36_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_37_OFFS 0x125000
#define QIB_7322_SendBufMA_37_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_37_OFFS 0x125800
#define QIB_7322_SendBufEA_37_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_38_OFFS 0x126000
#define QIB_7322_SendBufMA_38_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_38_OFFS 0x126800
#define QIB_7322_SendBufEA_38_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_39_OFFS 0x127000
#define QIB_7322_SendBufMA_39_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_39_OFFS 0x127800
#define QIB_7322_SendBufEA_39_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_40_OFFS 0x128000
#define QIB_7322_SendBufMA_40_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_40_OFFS 0x128800
#define QIB_7322_SendBufEA_40_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_41_OFFS 0x129000
#define QIB_7322_SendBufMA_41_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_41_OFFS 0x129800
#define QIB_7322_SendBufEA_41_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_42_OFFS 0x12A000
#define QIB_7322_SendBufMA_42_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_42_OFFS 0x12A800
#define QIB_7322_SendBufEA_42_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_43_OFFS 0x12B000
#define QIB_7322_SendBufMA_43_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_43_OFFS 0x12B800
#define QIB_7322_SendBufEA_43_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_44_OFFS 0x12C000
#define QIB_7322_SendBufMA_44_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_44_OFFS 0x12C800
#define QIB_7322_SendBufEA_44_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_45_OFFS 0x12D000
#define QIB_7322_SendBufMA_45_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_45_OFFS 0x12D800
#define QIB_7322_SendBufEA_45_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_46_OFFS 0x12E000
#define QIB_7322_SendBufMA_46_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_46_OFFS 0x12E800
#define QIB_7322_SendBufEA_46_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_47_OFFS 0x12F000
#define QIB_7322_SendBufMA_47_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_47_OFFS 0x12F800
#define QIB_7322_SendBufEA_47_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_48_OFFS 0x130000
#define QIB_7322_SendBufMA_48_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_48_OFFS 0x130800
#define QIB_7322_SendBufEA_48_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_49_OFFS 0x131000
#define QIB_7322_SendBufMA_49_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_49_OFFS 0x131800
#define QIB_7322_SendBufEA_49_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_50_OFFS 0x132000
#define QIB_7322_SendBufMA_50_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_50_OFFS 0x132800
#define QIB_7322_SendBufEA_50_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_51_OFFS 0x133000
#define QIB_7322_SendBufMA_51_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_51_OFFS 0x133800
#define QIB_7322_SendBufEA_51_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_52_OFFS 0x134000
#define QIB_7322_SendBufMA_52_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_52_OFFS 0x134800
#define QIB_7322_SendBufEA_52_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_53_OFFS 0x135000
#define QIB_7322_SendBufMA_53_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_53_OFFS 0x135800
#define QIB_7322_SendBufEA_53_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_54_OFFS 0x136000
#define QIB_7322_SendBufMA_54_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_54_OFFS 0x136800
#define QIB_7322_SendBufEA_54_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_55_OFFS 0x137000
#define QIB_7322_SendBufMA_55_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_55_OFFS 0x137800
#define QIB_7322_SendBufEA_55_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_56_OFFS 0x138000
#define QIB_7322_SendBufMA_56_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_56_OFFS 0x138800
#define QIB_7322_SendBufEA_56_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_57_OFFS 0x139000
#define QIB_7322_SendBufMA_57_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_57_OFFS 0x139800
#define QIB_7322_SendBufEA_57_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_58_OFFS 0x13A000
#define QIB_7322_SendBufMA_58_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_58_OFFS 0x13A800
#define QIB_7322_SendBufEA_58_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_59_OFFS 0x13B000
#define QIB_7322_SendBufMA_59_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_59_OFFS 0x13B800
#define QIB_7322_SendBufEA_59_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_60_OFFS 0x13C000
#define QIB_7322_SendBufMA_60_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_60_OFFS 0x13C800
#define QIB_7322_SendBufEA_60_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_61_OFFS 0x13D000
#define QIB_7322_SendBufMA_61_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_61_OFFS 0x13D800
#define QIB_7322_SendBufEA_61_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_62_OFFS 0x13E000
#define QIB_7322_SendBufMA_62_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_62_OFFS 0x13E800
#define QIB_7322_SendBufEA_62_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_63_OFFS 0x13F000
#define QIB_7322_SendBufMA_63_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_63_OFFS 0x13F800
#define QIB_7322_SendBufEA_63_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_64_OFFS 0x140000
#define QIB_7322_SendBufMA_64_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_64_OFFS 0x140800
#define QIB_7322_SendBufEA_64_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_65_OFFS 0x141000
#define QIB_7322_SendBufMA_65_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_65_OFFS 0x141800
#define QIB_7322_SendBufEA_65_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_66_OFFS 0x142000
#define QIB_7322_SendBufMA_66_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_66_OFFS 0x142800
#define QIB_7322_SendBufEA_66_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_67_OFFS 0x143000
#define QIB_7322_SendBufMA_67_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_67_OFFS 0x143800
#define QIB_7322_SendBufEA_67_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_68_OFFS 0x144000
#define QIB_7322_SendBufMA_68_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_68_OFFS 0x144800
#define QIB_7322_SendBufEA_68_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_69_OFFS 0x145000
#define QIB_7322_SendBufMA_69_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_69_OFFS 0x145800
#define QIB_7322_SendBufEA_69_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_70_OFFS 0x146000
#define QIB_7322_SendBufMA_70_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_70_OFFS 0x146800
#define QIB_7322_SendBufEA_70_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_71_OFFS 0x147000
#define QIB_7322_SendBufMA_71_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_71_OFFS 0x147800
#define QIB_7322_SendBufEA_71_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_72_OFFS 0x148000
#define QIB_7322_SendBufMA_72_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_72_OFFS 0x148800
#define QIB_7322_SendBufEA_72_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_73_OFFS 0x149000
#define QIB_7322_SendBufMA_73_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_73_OFFS 0x149800
#define QIB_7322_SendBufEA_73_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_74_OFFS 0x14A000
#define QIB_7322_SendBufMA_74_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_74_OFFS 0x14A800
#define QIB_7322_SendBufEA_74_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_75_OFFS 0x14B000
#define QIB_7322_SendBufMA_75_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_75_OFFS 0x14B800
#define QIB_7322_SendBufEA_75_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_76_OFFS 0x14C000
#define QIB_7322_SendBufMA_76_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_76_OFFS 0x14C800
#define QIB_7322_SendBufEA_76_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_77_OFFS 0x14D000
#define QIB_7322_SendBufMA_77_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_77_OFFS 0x14D800
#define QIB_7322_SendBufEA_77_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_78_OFFS 0x14E000
#define QIB_7322_SendBufMA_78_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_78_OFFS 0x14E800
#define QIB_7322_SendBufEA_78_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_79_OFFS 0x14F000
#define QIB_7322_SendBufMA_79_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_79_OFFS 0x14F800
#define QIB_7322_SendBufEA_79_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_80_OFFS 0x150000
#define QIB_7322_SendBufMA_80_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_80_OFFS 0x150800
#define QIB_7322_SendBufEA_80_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_81_OFFS 0x151000
#define QIB_7322_SendBufMA_81_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_81_OFFS 0x151800
#define QIB_7322_SendBufEA_81_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_82_OFFS 0x152000
#define QIB_7322_SendBufMA_82_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_82_OFFS 0x152800
#define QIB_7322_SendBufEA_82_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_83_OFFS 0x153000
#define QIB_7322_SendBufMA_83_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_83_OFFS 0x153800
#define QIB_7322_SendBufEA_83_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_84_OFFS 0x154000
#define QIB_7322_SendBufMA_84_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_84_OFFS 0x154800
#define QIB_7322_SendBufEA_84_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_85_OFFS 0x155000
#define QIB_7322_SendBufMA_85_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_85_OFFS 0x155800
#define QIB_7322_SendBufEA_85_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_86_OFFS 0x156000
#define QIB_7322_SendBufMA_86_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_86_OFFS 0x156800
#define QIB_7322_SendBufEA_86_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_87_OFFS 0x157000
#define QIB_7322_SendBufMA_87_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_87_OFFS 0x157800
#define QIB_7322_SendBufEA_87_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_88_OFFS 0x158000
#define QIB_7322_SendBufMA_88_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_88_OFFS 0x158800
#define QIB_7322_SendBufEA_88_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_89_OFFS 0x159000
#define QIB_7322_SendBufMA_89_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_89_OFFS 0x159800
#define QIB_7322_SendBufEA_89_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_90_OFFS 0x15A000
#define QIB_7322_SendBufMA_90_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_90_OFFS 0x15A800
#define QIB_7322_SendBufEA_90_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_91_OFFS 0x15B000
#define QIB_7322_SendBufMA_91_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_91_OFFS 0x15B800
#define QIB_7322_SendBufEA_91_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_92_OFFS 0x15C000
#define QIB_7322_SendBufMA_92_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_92_OFFS 0x15C800
#define QIB_7322_SendBufEA_92_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_93_OFFS 0x15D000
#define QIB_7322_SendBufMA_93_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_93_OFFS 0x15D800
#define QIB_7322_SendBufEA_93_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_94_OFFS 0x15E000
#define QIB_7322_SendBufMA_94_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_94_OFFS 0x15E800
#define QIB_7322_SendBufEA_94_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_95_OFFS 0x15F000
#define QIB_7322_SendBufMA_95_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_95_OFFS 0x15F800
#define QIB_7322_SendBufEA_95_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_96_OFFS 0x160000
#define QIB_7322_SendBufMA_96_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_96_OFFS 0x160800
#define QIB_7322_SendBufEA_96_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_97_OFFS 0x161000
#define QIB_7322_SendBufMA_97_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_97_OFFS 0x161800
#define QIB_7322_SendBufEA_97_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_98_OFFS 0x162000
#define QIB_7322_SendBufMA_98_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_98_OFFS 0x162800
#define QIB_7322_SendBufEA_98_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_99_OFFS 0x163000
#define QIB_7322_SendBufMA_99_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_99_OFFS 0x163800
#define QIB_7322_SendBufEA_99_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_100_OFFS 0x164000
#define QIB_7322_SendBufMA_100_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_100_OFFS 0x164800
#define QIB_7322_SendBufEA_100_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_101_OFFS 0x165000
#define QIB_7322_SendBufMA_101_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_101_OFFS 0x165800
#define QIB_7322_SendBufEA_101_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_102_OFFS 0x166000
#define QIB_7322_SendBufMA_102_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_102_OFFS 0x166800
#define QIB_7322_SendBufEA_102_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_103_OFFS 0x167000
#define QIB_7322_SendBufMA_103_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_103_OFFS 0x167800
#define QIB_7322_SendBufEA_103_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_104_OFFS 0x168000
#define QIB_7322_SendBufMA_104_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_104_OFFS 0x168800
#define QIB_7322_SendBufEA_104_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_105_OFFS 0x169000
#define QIB_7322_SendBufMA_105_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_105_OFFS 0x169800
#define QIB_7322_SendBufEA_105_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_106_OFFS 0x16A000
#define QIB_7322_SendBufMA_106_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_106_OFFS 0x16A800
#define QIB_7322_SendBufEA_106_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_107_OFFS 0x16B000
#define QIB_7322_SendBufMA_107_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_107_OFFS 0x16B800
#define QIB_7322_SendBufEA_107_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_108_OFFS 0x16C000
#define QIB_7322_SendBufMA_108_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_108_OFFS 0x16C800
#define QIB_7322_SendBufEA_108_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_109_OFFS 0x16D000
#define QIB_7322_SendBufMA_109_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_109_OFFS 0x16D800
#define QIB_7322_SendBufEA_109_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_110_OFFS 0x16E000
#define QIB_7322_SendBufMA_110_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_110_OFFS 0x16E800
#define QIB_7322_SendBufEA_110_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_111_OFFS 0x16F000
#define QIB_7322_SendBufMA_111_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_111_OFFS 0x16F800
#define QIB_7322_SendBufEA_111_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_112_OFFS 0x170000
#define QIB_7322_SendBufMA_112_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_112_OFFS 0x170800
#define QIB_7322_SendBufEA_112_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_113_OFFS 0x171000
#define QIB_7322_SendBufMA_113_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_113_OFFS 0x171800
#define QIB_7322_SendBufEA_113_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_114_OFFS 0x172000
#define QIB_7322_SendBufMA_114_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_114_OFFS 0x172800
#define QIB_7322_SendBufEA_114_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_115_OFFS 0x173000
#define QIB_7322_SendBufMA_115_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_115_OFFS 0x173800
#define QIB_7322_SendBufEA_115_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_116_OFFS 0x174000
#define QIB_7322_SendBufMA_116_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_116_OFFS 0x174800
#define QIB_7322_SendBufEA_116_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_117_OFFS 0x175000
#define QIB_7322_SendBufMA_117_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_117_OFFS 0x175800
#define QIB_7322_SendBufEA_117_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_118_OFFS 0x176000
#define QIB_7322_SendBufMA_118_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_118_OFFS 0x176800
#define QIB_7322_SendBufEA_118_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_119_OFFS 0x177000
#define QIB_7322_SendBufMA_119_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_119_OFFS 0x177800
#define QIB_7322_SendBufEA_119_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_120_OFFS 0x178000
#define QIB_7322_SendBufMA_120_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_120_OFFS 0x178800
#define QIB_7322_SendBufEA_120_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_121_OFFS 0x179000
#define QIB_7322_SendBufMA_121_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_121_OFFS 0x179800
#define QIB_7322_SendBufEA_121_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_122_OFFS 0x17A000
#define QIB_7322_SendBufMA_122_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_122_OFFS 0x17A800
#define QIB_7322_SendBufEA_122_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_123_OFFS 0x17B000
#define QIB_7322_SendBufMA_123_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_123_OFFS 0x17B800
#define QIB_7322_SendBufEA_123_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_124_OFFS 0x17C000
#define QIB_7322_SendBufMA_124_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_124_OFFS 0x17C800
#define QIB_7322_SendBufEA_124_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_125_OFFS 0x17D000
#define QIB_7322_SendBufMA_125_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_125_OFFS 0x17D800
#define QIB_7322_SendBufEA_125_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_126_OFFS 0x17E000
#define QIB_7322_SendBufMA_126_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_126_OFFS 0x17E800
#define QIB_7322_SendBufEA_126_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_127_OFFS 0x17F000
#define QIB_7322_SendBufMA_127_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_127_OFFS 0x17F800
#define QIB_7322_SendBufEA_127_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_128_OFFS 0x180000
#define QIB_7322_SendBufMA_128_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_128_OFFS 0x181000
#define QIB_7322_SendBufEA_128_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_129_OFFS 0x182000
#define QIB_7322_SendBufMA_129_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_129_OFFS 0x183000
#define QIB_7322_SendBufEA_129_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_130_OFFS 0x184000
#define QIB_7322_SendBufMA_130_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_130_OFFS 0x185000
#define QIB_7322_SendBufEA_130_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_131_OFFS 0x186000
#define QIB_7322_SendBufMA_131_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_131_OFFS 0x187000
#define QIB_7322_SendBufEA_131_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_132_OFFS 0x188000
#define QIB_7322_SendBufMA_132_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_132_OFFS 0x189000
#define QIB_7322_SendBufEA_132_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_133_OFFS 0x18A000
#define QIB_7322_SendBufMA_133_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_133_OFFS 0x18B000
#define QIB_7322_SendBufEA_133_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_134_OFFS 0x18C000
#define QIB_7322_SendBufMA_134_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_134_OFFS 0x18D000
#define QIB_7322_SendBufEA_134_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_135_OFFS 0x18E000
#define QIB_7322_SendBufMA_135_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_135_OFFS 0x18F000
#define QIB_7322_SendBufEA_135_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_136_OFFS 0x190000
#define QIB_7322_SendBufMA_136_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_136_OFFS 0x191000
#define QIB_7322_SendBufEA_136_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_137_OFFS 0x192000
#define QIB_7322_SendBufMA_137_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_137_OFFS 0x193000
#define QIB_7322_SendBufEA_137_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_138_OFFS 0x194000
#define QIB_7322_SendBufMA_138_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_138_OFFS 0x195000
#define QIB_7322_SendBufEA_138_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_139_OFFS 0x196000
#define QIB_7322_SendBufMA_139_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_139_OFFS 0x197000
#define QIB_7322_SendBufEA_139_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_140_OFFS 0x198000
#define QIB_7322_SendBufMA_140_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_140_OFFS 0x199000
#define QIB_7322_SendBufEA_140_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_141_OFFS 0x19A000
#define QIB_7322_SendBufMA_141_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_141_OFFS 0x19B000
#define QIB_7322_SendBufEA_141_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_142_OFFS 0x19C000
#define QIB_7322_SendBufMA_142_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_142_OFFS 0x19D000
#define QIB_7322_SendBufEA_142_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_143_OFFS 0x19E000
#define QIB_7322_SendBufMA_143_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_143_OFFS 0x19F000
#define QIB_7322_SendBufEA_143_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_144_OFFS 0x1A0000
#define QIB_7322_SendBufMA_144_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_144_OFFS 0x1A1000
#define QIB_7322_SendBufEA_144_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_145_OFFS 0x1A2000
#define QIB_7322_SendBufMA_145_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_145_OFFS 0x1A3000
#define QIB_7322_SendBufEA_145_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_146_OFFS 0x1A4000
#define QIB_7322_SendBufMA_146_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_146_OFFS 0x1A5000
#define QIB_7322_SendBufEA_146_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_147_OFFS 0x1A6000
#define QIB_7322_SendBufMA_147_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_147_OFFS 0x1A7000
#define QIB_7322_SendBufEA_147_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_148_OFFS 0x1A8000
#define QIB_7322_SendBufMA_148_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_148_OFFS 0x1A9000
#define QIB_7322_SendBufEA_148_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_149_OFFS 0x1AA000
#define QIB_7322_SendBufMA_149_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_149_OFFS 0x1AB000
#define QIB_7322_SendBufEA_149_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_150_OFFS 0x1AC000
#define QIB_7322_SendBufMA_150_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_150_OFFS 0x1AD000
#define QIB_7322_SendBufEA_150_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_151_OFFS 0x1AE000
#define QIB_7322_SendBufMA_151_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_151_OFFS 0x1AF000
#define QIB_7322_SendBufEA_151_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_152_OFFS 0x1B0000
#define QIB_7322_SendBufMA_152_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_152_OFFS 0x1B1000
#define QIB_7322_SendBufEA_152_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_153_OFFS 0x1B2000
#define QIB_7322_SendBufMA_153_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_153_OFFS 0x1B3000
#define QIB_7322_SendBufEA_153_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_154_OFFS 0x1B4000
#define QIB_7322_SendBufMA_154_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_154_OFFS 0x1B5000
#define QIB_7322_SendBufEA_154_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_155_OFFS 0x1B6000
#define QIB_7322_SendBufMA_155_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_155_OFFS 0x1B7000
#define QIB_7322_SendBufEA_155_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_156_OFFS 0x1B8000
#define QIB_7322_SendBufMA_156_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_156_OFFS 0x1B9000
#define QIB_7322_SendBufEA_156_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_157_OFFS 0x1BA000
#define QIB_7322_SendBufMA_157_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_157_OFFS 0x1BB000
#define QIB_7322_SendBufEA_157_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_158_OFFS 0x1BC000
#define QIB_7322_SendBufMA_158_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_158_OFFS 0x1BD000
#define QIB_7322_SendBufEA_158_DEF 0x0000000000000000

#define QIB_7322_SendBufMA_159_OFFS 0x1BE000
#define QIB_7322_SendBufMA_159_DEF 0x0000000000000000

#define QIB_7322_SendBufEA_159_OFFS 0x1BF000
#define QIB_7322_SendBufEA_159_DEF 0x0000000000000000

#define QIB_7322_SendBufVL15_0_OFFS 0x1C0000
#define QIB_7322_SendBufVL15_0_DEF 0x0000000000000000

#define QIB_7322_RcvHdrTail0_OFFS 0x200000
#define QIB_7322_RcvHdrTail0_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead0_OFFS 0x200008
#define QIB_7322_RcvHdrHead0_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead0_counter_LSB 0x20
#define QIB_7322_RcvHdrHead0_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead0_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead0_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead0_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead0_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail0_OFFS 0x200010
#define QIB_7322_RcvEgrIndexTail0_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead0_OFFS 0x200018
#define QIB_7322_RcvEgrIndexHead0_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable0_OFFS 0x201000
#define QIB_7322_RcvTIDFlowTable0_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable0_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable0_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable0_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable0_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable0_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable0_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable0_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable0_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable0_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable0_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable0_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable0_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail1_OFFS 0x210000
#define QIB_7322_RcvHdrTail1_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead1_OFFS 0x210008
#define QIB_7322_RcvHdrHead1_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead1_counter_LSB 0x20
#define QIB_7322_RcvHdrHead1_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead1_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead1_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead1_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead1_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail1_OFFS 0x210010
#define QIB_7322_RcvEgrIndexTail1_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead1_OFFS 0x210018
#define QIB_7322_RcvEgrIndexHead1_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable1_OFFS 0x211000
#define QIB_7322_RcvTIDFlowTable1_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable1_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable1_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable1_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable1_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable1_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable1_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable1_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable1_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable1_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable1_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable1_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable1_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable1_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable1_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable1_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable1_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable1_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable1_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable1_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable1_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable1_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable1_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable1_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable1_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail2_OFFS 0x220000
#define QIB_7322_RcvHdrTail2_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead2_OFFS 0x220008
#define QIB_7322_RcvHdrHead2_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead2_counter_LSB 0x20
#define QIB_7322_RcvHdrHead2_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead2_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead2_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead2_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead2_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail2_OFFS 0x220010
#define QIB_7322_RcvEgrIndexTail2_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead2_OFFS 0x220018
#define QIB_7322_RcvEgrIndexHead2_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable2_OFFS 0x221000
#define QIB_7322_RcvTIDFlowTable2_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable2_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable2_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable2_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable2_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable2_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable2_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable2_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable2_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable2_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable2_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable2_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable2_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable2_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable2_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable2_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable2_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable2_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable2_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable2_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable2_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable2_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable2_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable2_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable2_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail3_OFFS 0x230000
#define QIB_7322_RcvHdrTail3_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead3_OFFS 0x230008
#define QIB_7322_RcvHdrHead3_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead3_counter_LSB 0x20
#define QIB_7322_RcvHdrHead3_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead3_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead3_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead3_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead3_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail3_OFFS 0x230010
#define QIB_7322_RcvEgrIndexTail3_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead3_OFFS 0x230018
#define QIB_7322_RcvEgrIndexHead3_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable3_OFFS 0x231000
#define QIB_7322_RcvTIDFlowTable3_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable3_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable3_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable3_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable3_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable3_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable3_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable3_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable3_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable3_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable3_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable3_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable3_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable3_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable3_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable3_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable3_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable3_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable3_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable3_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable3_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable3_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable3_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable3_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable3_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail4_OFFS 0x240000
#define QIB_7322_RcvHdrTail4_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead4_OFFS 0x240008
#define QIB_7322_RcvHdrHead4_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead4_counter_LSB 0x20
#define QIB_7322_RcvHdrHead4_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead4_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead4_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead4_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead4_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail4_OFFS 0x240010
#define QIB_7322_RcvEgrIndexTail4_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead4_OFFS 0x240018
#define QIB_7322_RcvEgrIndexHead4_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable4_OFFS 0x241000
#define QIB_7322_RcvTIDFlowTable4_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable4_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable4_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable4_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable4_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable4_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable4_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable4_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable4_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable4_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable4_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable4_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable4_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable4_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable4_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable4_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable4_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable4_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable4_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable4_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable4_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable4_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable4_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable4_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable4_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail5_OFFS 0x250000
#define QIB_7322_RcvHdrTail5_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead5_OFFS 0x250008
#define QIB_7322_RcvHdrHead5_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead5_counter_LSB 0x20
#define QIB_7322_RcvHdrHead5_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead5_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead5_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead5_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead5_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail5_OFFS 0x250010
#define QIB_7322_RcvEgrIndexTail5_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead5_OFFS 0x250018
#define QIB_7322_RcvEgrIndexHead5_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable5_OFFS 0x251000
#define QIB_7322_RcvTIDFlowTable5_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable5_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable5_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable5_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable5_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable5_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable5_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable5_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable5_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable5_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable5_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable5_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable5_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable5_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable5_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable5_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable5_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable5_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable5_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable5_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable5_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable5_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable5_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable5_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable5_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail6_OFFS 0x260000
#define QIB_7322_RcvHdrTail6_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead6_OFFS 0x260008
#define QIB_7322_RcvHdrHead6_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead6_counter_LSB 0x20
#define QIB_7322_RcvHdrHead6_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead6_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead6_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead6_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead6_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail6_OFFS 0x260010
#define QIB_7322_RcvEgrIndexTail6_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead6_OFFS 0x260018
#define QIB_7322_RcvEgrIndexHead6_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable6_OFFS 0x261000
#define QIB_7322_RcvTIDFlowTable6_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable6_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable6_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable6_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable6_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable6_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable6_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable6_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable6_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable6_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable6_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable6_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable6_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable6_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable6_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable6_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable6_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable6_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable6_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable6_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable6_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable6_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable6_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable6_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable6_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail7_OFFS 0x270000
#define QIB_7322_RcvHdrTail7_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead7_OFFS 0x270008
#define QIB_7322_RcvHdrHead7_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead7_counter_LSB 0x20
#define QIB_7322_RcvHdrHead7_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead7_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead7_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead7_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead7_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail7_OFFS 0x270010
#define QIB_7322_RcvEgrIndexTail7_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead7_OFFS 0x270018
#define QIB_7322_RcvEgrIndexHead7_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable7_OFFS 0x271000
#define QIB_7322_RcvTIDFlowTable7_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable7_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable7_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable7_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable7_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable7_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable7_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable7_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable7_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable7_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable7_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable7_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable7_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable7_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable7_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable7_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable7_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable7_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable7_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable7_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable7_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable7_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable7_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable7_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable7_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail8_OFFS 0x280000
#define QIB_7322_RcvHdrTail8_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead8_OFFS 0x280008
#define QIB_7322_RcvHdrHead8_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead8_counter_LSB 0x20
#define QIB_7322_RcvHdrHead8_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead8_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead8_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead8_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead8_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail8_OFFS 0x280010
#define QIB_7322_RcvEgrIndexTail8_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead8_OFFS 0x280018
#define QIB_7322_RcvEgrIndexHead8_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable8_OFFS 0x281000
#define QIB_7322_RcvTIDFlowTable8_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable8_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable8_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable8_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable8_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable8_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable8_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable8_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable8_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable8_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable8_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable8_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable8_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable8_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable8_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable8_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable8_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable8_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable8_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable8_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable8_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable8_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable8_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable8_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable8_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail9_OFFS 0x290000
#define QIB_7322_RcvHdrTail9_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead9_OFFS 0x290008
#define QIB_7322_RcvHdrHead9_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead9_counter_LSB 0x20
#define QIB_7322_RcvHdrHead9_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead9_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead9_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead9_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead9_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail9_OFFS 0x290010
#define QIB_7322_RcvEgrIndexTail9_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead9_OFFS 0x290018
#define QIB_7322_RcvEgrIndexHead9_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable9_OFFS 0x291000
#define QIB_7322_RcvTIDFlowTable9_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable9_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable9_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable9_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable9_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable9_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable9_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable9_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable9_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable9_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable9_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable9_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable9_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable9_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable9_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable9_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable9_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable9_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable9_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable9_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable9_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable9_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable9_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable9_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable9_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail10_OFFS 0x2A0000
#define QIB_7322_RcvHdrTail10_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead10_OFFS 0x2A0008
#define QIB_7322_RcvHdrHead10_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead10_counter_LSB 0x20
#define QIB_7322_RcvHdrHead10_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead10_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead10_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead10_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead10_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail10_OFFS 0x2A0010
#define QIB_7322_RcvEgrIndexTail10_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead10_OFFS 0x2A0018
#define QIB_7322_RcvEgrIndexHead10_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable10_OFFS 0x2A1000
#define QIB_7322_RcvTIDFlowTable10_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable10_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable10_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable10_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable10_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable10_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable10_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable10_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable10_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable10_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable10_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable10_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable10_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable10_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable10_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable10_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable10_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable10_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable10_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable10_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable10_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable10_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable10_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable10_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable10_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail11_OFFS 0x2B0000
#define QIB_7322_RcvHdrTail11_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead11_OFFS 0x2B0008
#define QIB_7322_RcvHdrHead11_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead11_counter_LSB 0x20
#define QIB_7322_RcvHdrHead11_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead11_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead11_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead11_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead11_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail11_OFFS 0x2B0010
#define QIB_7322_RcvEgrIndexTail11_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead11_OFFS 0x2B0018
#define QIB_7322_RcvEgrIndexHead11_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable11_OFFS 0x2B1000
#define QIB_7322_RcvTIDFlowTable11_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable11_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable11_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable11_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable11_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable11_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable11_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable11_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable11_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable11_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable11_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable11_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable11_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable11_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable11_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable11_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable11_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable11_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable11_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable11_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable11_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable11_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable11_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable11_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable11_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail12_OFFS 0x2C0000
#define QIB_7322_RcvHdrTail12_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead12_OFFS 0x2C0008
#define QIB_7322_RcvHdrHead12_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead12_counter_LSB 0x20
#define QIB_7322_RcvHdrHead12_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead12_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead12_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead12_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead12_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail12_OFFS 0x2C0010
#define QIB_7322_RcvEgrIndexTail12_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead12_OFFS 0x2C0018
#define QIB_7322_RcvEgrIndexHead12_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable12_OFFS 0x2C1000
#define QIB_7322_RcvTIDFlowTable12_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable12_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable12_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable12_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable12_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable12_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable12_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable12_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable12_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable12_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable12_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable12_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable12_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable12_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable12_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable12_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable12_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable12_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable12_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable12_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable12_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable12_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable12_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable12_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable12_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail13_OFFS 0x2D0000
#define QIB_7322_RcvHdrTail13_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead13_OFFS 0x2D0008
#define QIB_7322_RcvHdrHead13_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead13_counter_LSB 0x20
#define QIB_7322_RcvHdrHead13_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead13_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead13_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead13_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead13_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail13_OFFS 0x2D0010
#define QIB_7322_RcvEgrIndexTail13_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead13_OFFS 0x2D0018
#define QIB_7322_RcvEgrIndexHead13_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable13_OFFS 0x2D1000
#define QIB_7322_RcvTIDFlowTable13_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable13_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable13_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable13_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable13_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable13_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable13_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable13_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable13_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable13_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable13_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable13_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable13_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable13_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable13_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable13_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable13_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable13_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable13_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable13_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable13_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable13_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable13_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable13_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable13_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail14_OFFS 0x2E0000
#define QIB_7322_RcvHdrTail14_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead14_OFFS 0x2E0008
#define QIB_7322_RcvHdrHead14_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead14_counter_LSB 0x20
#define QIB_7322_RcvHdrHead14_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead14_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead14_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead14_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead14_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail14_OFFS 0x2E0010
#define QIB_7322_RcvEgrIndexTail14_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead14_OFFS 0x2E0018
#define QIB_7322_RcvEgrIndexHead14_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable14_OFFS 0x2E1000
#define QIB_7322_RcvTIDFlowTable14_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable14_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable14_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable14_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable14_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable14_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable14_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable14_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable14_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable14_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable14_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable14_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable14_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable14_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable14_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable14_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable14_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable14_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable14_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable14_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable14_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable14_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable14_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable14_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable14_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail15_OFFS 0x2F0000
#define QIB_7322_RcvHdrTail15_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead15_OFFS 0x2F0008
#define QIB_7322_RcvHdrHead15_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead15_counter_LSB 0x20
#define QIB_7322_RcvHdrHead15_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead15_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead15_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead15_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead15_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail15_OFFS 0x2F0010
#define QIB_7322_RcvEgrIndexTail15_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead15_OFFS 0x2F0018
#define QIB_7322_RcvEgrIndexHead15_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable15_OFFS 0x2F1000
#define QIB_7322_RcvTIDFlowTable15_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable15_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable15_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable15_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable15_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable15_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable15_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable15_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable15_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable15_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable15_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable15_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable15_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable15_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable15_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable15_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable15_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable15_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable15_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable15_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable15_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable15_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable15_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable15_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable15_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail16_OFFS 0x300000
#define QIB_7322_RcvHdrTail16_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead16_OFFS 0x300008
#define QIB_7322_RcvHdrHead16_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead16_counter_LSB 0x20
#define QIB_7322_RcvHdrHead16_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead16_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead16_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead16_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead16_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail16_OFFS 0x300010
#define QIB_7322_RcvEgrIndexTail16_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead16_OFFS 0x300018
#define QIB_7322_RcvEgrIndexHead16_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable16_OFFS 0x301000
#define QIB_7322_RcvTIDFlowTable16_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable16_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable16_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable16_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable16_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable16_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable16_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable16_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable16_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable16_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable16_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable16_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable16_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable16_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable16_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable16_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable16_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable16_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable16_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable16_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable16_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable16_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable16_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable16_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable16_SeqNum_RMASK 0x7FF

#define QIB_7322_RcvHdrTail17_OFFS 0x310000
#define QIB_7322_RcvHdrTail17_DEF 0x0000000000000000

#define QIB_7322_RcvHdrHead17_OFFS 0x310008
#define QIB_7322_RcvHdrHead17_DEF 0x0000000000000000
#define QIB_7322_RcvHdrHead17_counter_LSB 0x20
#define QIB_7322_RcvHdrHead17_counter_MSB 0x2F
#define QIB_7322_RcvHdrHead17_counter_RMASK 0xFFFF
#define QIB_7322_RcvHdrHead17_RcvHeadPointer_LSB 0x0
#define QIB_7322_RcvHdrHead17_RcvHeadPointer_MSB 0x1F
#define QIB_7322_RcvHdrHead17_RcvHeadPointer_RMASK 0xFFFFFFFF

#define QIB_7322_RcvEgrIndexTail17_OFFS 0x310010
#define QIB_7322_RcvEgrIndexTail17_DEF 0x0000000000000000

#define QIB_7322_RcvEgrIndexHead17_OFFS 0x310018
#define QIB_7322_RcvEgrIndexHead17_DEF 0x0000000000000000

#define QIB_7322_RcvTIDFlowTable17_OFFS 0x311000
#define QIB_7322_RcvTIDFlowTable17_DEF 0x0000000000000000
#define QIB_7322_RcvTIDFlowTable17_GenMismatch_LSB 0x1C
#define QIB_7322_RcvTIDFlowTable17_GenMismatch_MSB 0x1C
#define QIB_7322_RcvTIDFlowTable17_GenMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable17_SeqMismatch_LSB 0x1B
#define QIB_7322_RcvTIDFlowTable17_SeqMismatch_MSB 0x1B
#define QIB_7322_RcvTIDFlowTable17_SeqMismatch_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable17_KeepOnGenErr_LSB 0x16
#define QIB_7322_RcvTIDFlowTable17_KeepOnGenErr_MSB 0x16
#define QIB_7322_RcvTIDFlowTable17_KeepOnGenErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable17_KeepAfterSeqErr_LSB 0x15
#define QIB_7322_RcvTIDFlowTable17_KeepAfterSeqErr_MSB 0x15
#define QIB_7322_RcvTIDFlowTable17_KeepAfterSeqErr_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable17_HdrSuppEnabled_LSB 0x14
#define QIB_7322_RcvTIDFlowTable17_HdrSuppEnabled_MSB 0x14
#define QIB_7322_RcvTIDFlowTable17_HdrSuppEnabled_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable17_FlowValid_LSB 0x13
#define QIB_7322_RcvTIDFlowTable17_FlowValid_MSB 0x13
#define QIB_7322_RcvTIDFlowTable17_FlowValid_RMASK 0x1
#define QIB_7322_RcvTIDFlowTable17_GenVal_LSB 0xB
#define QIB_7322_RcvTIDFlowTable17_GenVal_MSB 0x12
#define QIB_7322_RcvTIDFlowTable17_GenVal_RMASK 0xFF
#define QIB_7322_RcvTIDFlowTable17_SeqNum_LSB 0x0
#define QIB_7322_RcvTIDFlowTable17_SeqNum_MSB 0xA
#define QIB_7322_RcvTIDFlowTable17_SeqNum_RMASK 0x7FF
